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Don't use %g0 to materialize 0 directly.

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The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-05-19 21:47:13 +00:00
parent 60abcb786e
commit 634123e98d
4 changed files with 14 additions and 5 deletions
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2
lib/Target/Sparc/README.txt
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@ -57,3 +57,5 @@ int %t1(int %a, int %b) {
* Fill delay slots * Fill delay slots
* Implement JIT support * Implement JIT support
* Use %g0 directly to materialize 0. No instruction is required.

4
lib/Target/Sparc/SparcInstr64Bit.td
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@ -59,10 +59,6 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
// preferable to use a constant pool load instead, depending on the // preferable to use a constant pool load instead, depending on the
// microarchitecture. // microarchitecture.
// The %g0 register is constant 0.
// This is useful for stx %g0, [...], for example.
def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>;
// Single-instruction patterns. // Single-instruction patterns.
// The ALU instructions want their simm13 operands as i32 immediates. // The ALU instructions want their simm13 operands as i32 immediates.

2
test/CodeGen/SPARC/64bit.ll
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@ -26,7 +26,7 @@ define i64 @sra_reg(i64 %a, i64 %b) {
; restore %g0, %g0, %o0 ; restore %g0, %g0, %o0
; ;
; CHECK: ret_imm0 ; CHECK: ret_imm0
; CHECK: or %g0, %g0, %i0 ; CHECK: or %g0, 0, %i0
define i64 @ret_imm0() { define i64 @ret_imm0() {
ret i64 0 ret i64 0
} }

11
test/CodeGen/SPARC/64cond.ll
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@ -98,3 +98,14 @@ entry:
%rv = select i1 %tobool, double %a, double %b %rv = select i1 %tobool, double %a, double %b
ret double %rv ret double %rv
} }
; The MOVXCC instruction can't use %g0 for its tied operand.
; CHECK: select_consti64_xcc
; CHECK: subcc
; CHECK: movg %xcc, 123, %i0
define i64 @select_consti64_xcc(i64 %x, i64 %y) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i64 123, i64 0
ret i64 %rv
}