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FastISel support for AND and OR with type i1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55846 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-05 18:44:22 +00:00
parent 59e577f73c
commit 638c6830c6
1 changed files with 10 additions and 2 deletions
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10
lib/CodeGen/SelectionDAG/FastISel.cpp
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@ -103,12 +103,20 @@ bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
if (VT == MVT::Other || !VT.isSimple()) if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail. // Unhandled type. Halt "fast" selection and bail.
return false; return false;
// We only handle legal types. For example, on x86-32 the instruction // We only handle legal types. For example, on x86-32 the instruction
// selector contains all of the 64-bit instructions from x86-64, // selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't // under the assumption that i64 won't be used if the target doesn't
// support it. // support it.
if (!TLI.isTypeLegal(VT)) if (!TLI.isTypeLegal(VT)) {
// MVT::i1 is special. Allow AND and OR (but not XOR) because they
// don't require additional zeroing, which makes them easy.
if (VT == MVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
VT = TLI.getTypeToTransformTo(VT);
else
return false; return false;
}
unsigned Op0 = getRegForValue(I->getOperand(0)); unsigned Op0 = getRegForValue(I->getOperand(0));
if (Op0 == 0) if (Op0 == 0)