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FastISel support for AND and OR with type i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55846 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -103,12 +103,20 @@ bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
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if (VT == MVT::Other || !VT.isSimple())
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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return false;
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// We only handle legal types. For example, on x86-32 the instruction
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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// support it.
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if (!TLI.isTypeLegal(VT))
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if (!TLI.isTypeLegal(VT)) {
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return false;
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// MVT::i1 is special. Allow AND and OR (but not XOR) because they
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// don't require additional zeroing, which makes them easy.
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if (VT == MVT::i1 &&
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(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
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VT = TLI.getTypeToTransformTo(VT);
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else
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return false;
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}
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unsigned Op0 = getRegForValue(I->getOperand(0));
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unsigned Op0 = getRegForValue(I->getOperand(0));
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if (Op0 == 0)
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if (Op0 == 0)
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