mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Remove spurious mask operations from AArch64 add->compares on 16 and 8 bit values
This patch checks for DAG patterns that are an add or a sub followed by a compare on 16 and 8 bit inputs. Since AArch64 does not support those types natively they are legalized into 32 bit values, which means that mask operations are inserted into the DAG to emulate overflow behaviour. In many cases those masks do not change the result of the processing and just introduce a dependent operation, often in the middle of a hot loop. This patch detects the relevent DAG patterns and then tests to see if the transforms are equivalent with and without the mask, removing the mask if possible. The exact mechanism of this patch was discusses in http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-July/074444.html There is a reasonably good chance there are missed oppurtunities due to similiar (but not identical) DAG patterns that could be funneled into this test, adding them should be simple if we see test cases. Tests included. rdar://13754426 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216776 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Louis Gerbarg
parent
1469e29334
commit
6393b3a677
@ -7903,10 +7903,271 @@ static SDValue performNEONPostLDSTCombine(SDNode *N,
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return SDValue();
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}
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// Checks to see if the value is the prescribed width and returns information
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// about its extension mode.
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static
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bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
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ExtType = ISD::NON_EXTLOAD;
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switch(V.getNode()->getOpcode()) {
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default:
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return false;
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case ISD::LOAD: {
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LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
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if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
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|| (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
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ExtType = LoadNode->getExtensionType();
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return true;
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}
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return false;
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}
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case ISD::AssertSext: {
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VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
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if ((TypeNode->getVT() == MVT::i8 && width == 8)
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|| (TypeNode->getVT() == MVT::i16 && width == 16)) {
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ExtType = ISD::SEXTLOAD;
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return true;
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}
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return false;
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}
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case ISD::AssertZext: {
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VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
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if ((TypeNode->getVT() == MVT::i8 && width == 8)
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|| (TypeNode->getVT() == MVT::i16 && width == 16)) {
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ExtType = ISD::ZEXTLOAD;
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return true;
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}
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return false;
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}
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case ISD::Constant:
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case ISD::TargetConstant: {
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if(abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) < 1<<(width-1))
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return true;
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return false;
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}
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}
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return true;
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}
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// This function does a whole lot of voodoo to determine if the tests are
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// equivalent without and with a mask. Essentially what happens is that given a
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// DAG resembling:
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//
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// +-------------+ +-------------+ +-------------+ +-------------+
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// | Input | | AddConstant | | CompConstant| | CC |
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// +-------------+ +-------------+ +-------------+ +-------------+
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// | | | |
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// V V | +----------+
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// +-------------+ +----+ | |
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// | ADD | |0xff| | |
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// +-------------+ +----+ | |
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// | | | |
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// V V | |
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// +-------------+ | |
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// | AND | | |
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// +-------------+ | |
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// | | |
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// +-----+ | |
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// | | |
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// V V V
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// +-------------+
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// | CMP |
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// +-------------+
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//
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// The AND node may be safely removed for some combinations of inputs. In
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// particular we need to take into account the extension type of the Input,
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// the exact values of AddConstant, CompConstant, and CC, along with the nominal
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// width of the input (this can work for any width inputs, the above graph is
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// specific to 8 bits.
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//
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// The specific equations were worked out by generating output tables for each
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// AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
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// problem was simplified by working with 4 bit inputs, which means we only
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// needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
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// extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
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// patterns present in both extensions (0,7). For every distinct set of
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// AddConstant and CompConstants bit patterns we can consider the masked and
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// unmasked versions to be equivalent if the result of this function is true for
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// all 16 distinct bit patterns of for the current extension type of Input (w0).
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//
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// sub w8, w0, w1
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// and w10, w8, #0x0f
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// cmp w8, w2
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// cset w9, AArch64CC
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// cmp w10, w2
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// cset w11, AArch64CC
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// cmp w9, w11
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// cset w0, eq
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// ret
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//
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// Since the above function shows when the outputs are equivalent it defines
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// when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
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// would be expensive to run during compiles. The equations below were written
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// in a test harness that confirmed they gave equivalent outputs to the above
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// for all inputs function, so they can be used determine if the removal is
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// legal instead.
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//
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// isEquivalentMaskless() is the code for testing if the AND can be removed
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// factored out of the DAG recognition as the DAG can take several forms.
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static
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bool isEquivalentMaskless(unsigned CC, unsigned width,
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ISD::LoadExtType ExtType, signed AddConstant,
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signed CompConstant) {
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// By being careful about our equations and only writing the in term
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// symbolic values and well known constants (0, 1, -1, MaxUInt) we can
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// make them generally applicable to all bit widths.
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signed MaxUInt = (1 << width);
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// For the purposes of these comparisons sign extending the type is
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// equivalent to zero extending the add and displacing it by half the integer
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// width. Provided we are careful and make sure our equations are valid over
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// the whole range we can just adjust the input and avoid writing equations
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// for sign extended inputs.
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if (ExtType == ISD::SEXTLOAD)
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AddConstant -= (1 << (width-1));
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switch(CC) {
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case AArch64CC::LE:
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case AArch64CC::GT: {
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if ((AddConstant == 0) ||
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(CompConstant == MaxUInt - 1 && AddConstant < 0) ||
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(AddConstant >= 0 && CompConstant < 0) ||
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(AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
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return true;
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} break;
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case AArch64CC::LT:
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case AArch64CC::GE: {
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if ((AddConstant == 0) ||
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(AddConstant >= 0 && CompConstant <= 0) ||
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(AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
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return true;
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} break;
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case AArch64CC::HI:
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case AArch64CC::LS: {
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if ((AddConstant >= 0 && CompConstant < 0) ||
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(AddConstant <= 0 && CompConstant >= -1 &&
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CompConstant < AddConstant + MaxUInt))
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return true;
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} break;
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case AArch64CC::PL:
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case AArch64CC::MI: {
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if ((AddConstant == 0) ||
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(AddConstant > 0 && CompConstant <= 0) ||
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(AddConstant < 0 && CompConstant <= AddConstant))
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return true;
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} break;
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case AArch64CC::LO:
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case AArch64CC::HS: {
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if ((AddConstant >= 0 && CompConstant <= 0) ||
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(AddConstant <= 0 && CompConstant >= 0 &&
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CompConstant <= AddConstant + MaxUInt))
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return true;
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} break;
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case AArch64CC::EQ:
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case AArch64CC::NE: {
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if ((AddConstant > 0 && CompConstant < 0) ||
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(AddConstant < 0 && CompConstant >= 0 &&
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CompConstant < AddConstant + MaxUInt) ||
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(AddConstant >= 0 && CompConstant >= 0 &&
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CompConstant >= AddConstant) ||
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(AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
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return true;
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} break;
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case AArch64CC::VS:
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case AArch64CC::VC:
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case AArch64CC::AL:
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case AArch64CC::NV:
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return true;
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case AArch64CC::Invalid:
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break;
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}
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return false;
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}
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static
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SDValue performCONDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG, unsigned CCIndex,
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unsigned CmpIndex) {
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unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
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SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
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unsigned CondOpcode = SubsNode->getOpcode();
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if (CondOpcode != AArch64ISD::SUBS)
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return SDValue();
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// There is a SUBS feeding this condition. Is it fed by a mask we can
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// use?
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SDNode *AndNode = SubsNode->getOperand(0).getNode();
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unsigned MaskBits = 0;
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if (AndNode->getOpcode() != ISD::AND)
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return SDValue();
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
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uint32_t CNV = CN->getZExtValue();
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if (CNV == 255)
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MaskBits = 8;
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else if (CNV == 65535)
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MaskBits = 16;
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}
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if (!MaskBits)
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return SDValue();
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SDValue AddValue = AndNode->getOperand(0);
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if (AddValue.getOpcode() != ISD::ADD)
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return SDValue();
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// The basic dag structure is correct, grab the inputs and validate them.
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SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
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SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
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SDValue SubsInputValue = SubsNode->getOperand(1);
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// The mask is present and the provenance of all the values is a smaller type,
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// lets see if the mask is superfluous.
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if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
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!isa<ConstantSDNode>(SubsInputValue.getNode()))
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return SDValue();
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ISD::LoadExtType ExtType;
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if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
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!checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
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!checkValueWidth(AddInputValue1, MaskBits, ExtType) )
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return SDValue();
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if(!isEquivalentMaskless(CC, MaskBits, ExtType,
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cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
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cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
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return SDValue();
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// The AND is not necessary, remove it.
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SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
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SubsNode->getValueType(1));
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SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
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SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
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DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
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return SDValue(N, 0);
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}
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// Optimize compare with zero and branch.
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static SDValue performBRCONDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG) {
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SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
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if (NV.getNode())
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N = NV.getNode();
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SDValue Chain = N->getOperand(0);
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SDValue Dest = N->getOperand(1);
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SDValue CCVal = N->getOperand(2);
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@ -8063,6 +8324,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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return performSTORECombine(N, DCI, DAG, Subtarget);
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case AArch64ISD::BRCOND:
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return performBRCONDCombine(N, DCI, DAG);
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case AArch64ISD::CSEL:
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return performCONDCombine(N, DCI, DAG, 2, 3);
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case AArch64ISD::DUP:
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return performPostLD1Combine(N, DCI, false);
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case ISD::INSERT_VECTOR_ELT:
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269
test/CodeGen/AArch64/and-mask-removal.ll
Normal file
269
test/CodeGen/AArch64/and-mask-removal.ll
Normal file
@ -0,0 +1,269 @@
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; RUN: llc -O0 -fast-isel=false -mtriple=arm64-apple-darwin < %s | FileCheck %s
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@board = common global [400 x i8] zeroinitializer, align 1
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@next_string = common global i32 0, align 4
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@string_number = common global [400 x i32] zeroinitializer, align 4
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; Function Attrs: nounwind ssp
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define void @new_position(i32 %pos) {
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entry:
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%idxprom = sext i32 %pos to i64
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%arrayidx = getelementptr inbounds [400 x i8]* @board, i64 0, i64 %idxprom
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%tmp = load i8* %arrayidx, align 1
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%.off = add i8 %tmp, -1
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%switch = icmp ult i8 %.off, 2
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br i1 %switch, label %if.then, label %if.end
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if.then: ; preds = %entry
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%tmp1 = load i32* @next_string, align 4
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%arrayidx8 = getelementptr inbounds [400 x i32]* @string_number, i64 0, i64 %idxprom
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store i32 %tmp1, i32* %arrayidx8, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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; CHECK-LABEL: new_position
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_0(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 74
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%1 = icmp ult i8 %0, -20
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_0
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test8_1(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 246
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%1 = icmp uge i8 %0, 90
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_1
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_2(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 227
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%1 = icmp ne i8 %0, 179
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_2
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_3(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 201
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%1 = icmp eq i8 %0, 154
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_3
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_4(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, -79
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%1 = icmp ne i8 %0, -40
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_4
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_5(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 133
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%1 = icmp uge i8 %0, -105
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_5
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test8_6(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, -58
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%1 = icmp uge i8 %0, 155
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_6
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test8_7(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 225
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%1 = icmp ult i8 %0, 124
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_7
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_8(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 190
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%1 = icmp uge i8 %0, 1
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_8
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test16_0(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, -46989
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%1 = icmp ne i16 %0, -41903
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_0
|
||||
; CHECK-NOT: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_2(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, 16882
|
||||
%1 = icmp ule i16 %0, -24837
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_2
|
||||
; CHECK: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_3(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, 29283
|
||||
%1 = icmp ne i16 %0, 16947
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_3
|
||||
; CHECK-NOT: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_4(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, -35551
|
||||
%1 = icmp uge i16 %0, 15677
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_4
|
||||
; CHECK: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_5(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, -25214
|
||||
%1 = icmp ne i16 %0, -1932
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_5
|
||||
; CHECK-NOT: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_6(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, -32194
|
||||
%1 = icmp uge i16 %0, -41215
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_6
|
||||
; CHECK-NOT: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_7(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, 9272
|
||||
%1 = icmp uge i16 %0, -42916
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_7
|
||||
; CHECK: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
define zeroext i1 @test16_8(i16 zeroext %x) align 2 {
|
||||
entry:
|
||||
%0 = add i16 %x, -63749
|
||||
%1 = icmp ne i16 %0, 6706
|
||||
br i1 %1, label %ret_true, label %ret_false
|
||||
ret_false:
|
||||
ret i1 false
|
||||
ret_true:
|
||||
ret i1 true
|
||||
; CHECK-LABEL: test16_8
|
||||
; CHECK-NOT: and
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user