[AVX512] Implemented AVX512VL FP bnary packed instructions (VADDP*, VSUBP*, VMULP*, VDIVP*, VMAXP*, VMINP*)
Refactored through AVX512_maskable Added encoding tests for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220858 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
7710e2553b
commit
63c2f3292e
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@ -2984,118 +2984,58 @@ defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
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}
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multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass KRC,
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RegisterClass RC, ValueType vt,
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X86MemOperand x86memop, PatFrag mem_frag,
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X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
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string BrdcstStr,
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Domain d, OpndItins itins, bit commutable> {
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let isCommutable = commutable in {
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
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EVEX_4V;
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def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
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[], itins.rr, d>, EVEX_4V, EVEX_K;
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def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
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[], itins.rr, d>, EVEX_4V, EVEX_KZ;
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}
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X86VectorVTInfo _, bit IsCommutable> {
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defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
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let mayLoad = 1 in {
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
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itins.rm, d>, EVEX_4V;
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defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
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defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(OpNode _.RC:$src1, (_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2))))>,
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EVEX_4V, EVEX_B;
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}//let mayLoad = 1
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}
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def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
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", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1,
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(vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
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itins.rm, d>, EVEX_4V, EVEX_B;
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multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit IsCommutable = 0> {
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defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
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IsCommutable>, EVEX_V512, PS,
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EVEX_CD8<32, CD8VF>;
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defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
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IsCommutable>, EVEX_V512, PD, VEX_W,
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EVEX_CD8<64, CD8VF>;
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def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], itins.rm, d>, EVEX_4V, EVEX_K;
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def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
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[], itins.rm, d>, EVEX_4V, EVEX_KZ;
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def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
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" \t{${src2}", BrdcstStr,
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", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
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[], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
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def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
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" \t{${src2}", BrdcstStr,
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", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
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BrdcstStr, "}"),
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[], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
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// Define only if AVX512VL feature is present.
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let Predicates = [HasVLX] in {
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defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
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IsCommutable>, EVEX_V128, PS,
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EVEX_CD8<32, CD8VF>;
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defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
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IsCommutable>, EVEX_V256, PS,
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EVEX_CD8<32, CD8VF>;
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defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
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IsCommutable>, EVEX_V128, PD, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
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IsCommutable>, EVEX_V256, PD, VEX_W,
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EVEX_CD8<64, CD8VF>;
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}
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}
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defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 1>,
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EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 1>,
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EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>,
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EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>,
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EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 1>,
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EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 1>,
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EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 0>,
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EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 0>,
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EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
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defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
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defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
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defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
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defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
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defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
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def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
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(v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
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