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ARMLoadStoreOptimizer: Code cleanup; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238289 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -447,8 +447,7 @@ ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
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if (InsertSub) {
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if (InsertSub) {
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// An instruction above couldn't be updated, so insert a sub.
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// An instruction above couldn't be updated, so insert a sub.
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base), true)
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base), true)
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.addReg(Base, getKillRegState(false)).addImm(WordOffset * 4)
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.addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
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.addImm(Pred).addReg(PredReg);
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return;
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return;
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}
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}
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@ -466,8 +465,7 @@ ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
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if (MBBI != MBB.end()) --MBBI;
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if (MBBI != MBB.end()) --MBBI;
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AddDefaultT1CC(
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AddDefaultT1CC(
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BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base), true)
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BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base), true)
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.addReg(Base, getKillRegState(false)).addImm(WordOffset * 4)
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.addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
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.addImm(Pred).addReg(PredReg);
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}
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}
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}
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}
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@ -499,8 +497,8 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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// non-writeback.
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// non-writeback.
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// It's also not possible to merge an STR of the base register in Thumb1.
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// It's also not possible to merge an STR of the base register in Thumb1.
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if (isThumb1)
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if (isThumb1)
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for (unsigned I = 0; I < NumRegs; ++I)
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for (const std::pair<unsigned, bool> &R : Regs)
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if (Base == Regs[I].first) {
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if (Base == R.first) {
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assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
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assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
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if (Opcode == ARM::tLDRi) {
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if (Opcode == ARM::tLDRi) {
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Writeback = false;
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Writeback = false;
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@ -656,13 +654,13 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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MIB.addImm(Pred).addReg(PredReg);
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MIB.addImm(Pred).addReg(PredReg);
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for (unsigned i = 0; i != NumRegs; ++i)
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for (const std::pair<unsigned, bool> &R : Regs)
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MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
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MIB = MIB.addReg(R.first, getDefRegState(isDef)
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| getKillRegState(Regs[i].second));
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| getKillRegState(R.second));
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// Add implicit defs for super-registers.
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// Add implicit defs for super-registers.
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for (unsigned i = 0, e = ImpDefs.size(); i != e; ++i)
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for (unsigned ImpDef : ImpDefs)
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MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
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MIB.addReg(ImpDef, RegState::ImplicitDefine);
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return true;
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return true;
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}
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}
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@ -919,7 +917,7 @@ static bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
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case ARM::t2SUBri:
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case ARM::t2SUBri:
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case ARM::SUBri:
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case ARM::SUBri:
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CheckCPSRDef = true;
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CheckCPSRDef = true;
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// fallthrough
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break;
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case ARM::tSUBspi:
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case ARM::tSUBspi:
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break;
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break;
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}
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}
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@ -954,7 +952,7 @@ static bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
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case ARM::t2ADDri:
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case ARM::t2ADDri:
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case ARM::ADDri:
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case ARM::ADDri:
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CheckCPSRDef = true;
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CheckCPSRDef = true;
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// fallthrough
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break;
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case ARM::tADDspi:
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case ARM::tADDspi:
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break;
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break;
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}
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}
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@ -1612,7 +1610,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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bool Advance = false;
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bool Advance = false;
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bool TryMerge = false;
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bool TryMerge = false;
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bool Clobber = false;
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bool isMemOp = isMemoryOp(MBBI);
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bool isMemOp = isMemoryOp(MBBI);
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if (isMemOp) {
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if (isMemOp) {
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@ -1634,7 +1631,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// looks like the later ldr(s) use the same base register. Try to
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// looks like the later ldr(s) use the same base register. Try to
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// merge the ldr's so far, including this one. But don't try to
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// merge the ldr's so far, including this one. But don't try to
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// combine the following ldr(s).
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// combine the following ldr(s).
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Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
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bool Clobber = isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg();
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// Watch out for:
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// Watch out for:
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// r4 := ldr [r0, #8]
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// r4 := ldr [r0, #8]
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