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R600/SI: Fix formatting.

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Avoid weird line wrapping of BuildMI dest register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-08-02 01:10:28 +00:00
parent a272803ec5
commit 63fab54fac
1 changed files with 28 additions and 22 deletions
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26
lib/Target/R600/SIISelLowering.cpp
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@@ -587,12 +587,14 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
unsigned DestReg = MI->getOperand(0).getReg();
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg) BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
.addImm(0x7fffffff); .addImm(0x7fffffff);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32), BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
.addReg(Reg); .addReg(Reg);
MI->eraseFromParent(); MI->eraseFromParent();
@@ -602,12 +604,14 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
unsigned DestReg = MI->getOperand(0).getReg();
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg) BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
.addImm(0x80000000); .addImm(0x80000000);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32), BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
.addReg(Reg); .addReg(Reg);
MI->eraseFromParent(); MI->eraseFromParent();
@@ -616,8 +620,10 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
case AMDGPU::FCLAMP_SI: { case AMDGPU::FCLAMP_SI: {
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
MI->getOperand(0).getReg()) DebugLoc DL = MI->getDebugLoc();
unsigned DestReg = MI->getOperand(0).getReg();
BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
.addImm(0) // SRC0 modifiers .addImm(0) // SRC0 modifiers
.addOperand(MI->getOperand(1)) .addOperand(MI->getOperand(1))
.addImm(0) // SRC1 modifiers .addImm(0) // SRC1 modifiers