6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-03 00:33:09 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Fix formatting.

Browse Source 
Avoid weird line wrapping of BuildMI dest register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-08-02 01:10:28 +00:00
parent a272803ec5
commit 63fab54fac
1 changed files with 28 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
lib/Target/R600/SIISelLowering.cpp
View File

@ -587,14 +587,16 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
unsigned DestReg = MI->getOperand(0).getReg();
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg) BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
.addImm(0x7fffffff); .addImm(0x7fffffff);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32), BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg())
.addReg(MI->getOperand(1).getReg()) .addReg(Reg);
.addReg(Reg);
MI->eraseFromParent(); MI->eraseFromParent();
break; break;
} }
@ -602,28 +604,32 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
unsigned DestReg = MI->getOperand(0).getReg();
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg) BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
.addImm(0x80000000); .addImm(0x80000000);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32), BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg())
.addReg(MI->getOperand(1).getReg()) .addReg(Reg);
.addReg(Reg);
MI->eraseFromParent(); MI->eraseFromParent();
break; break;
} }
case AMDGPU::FCLAMP_SI: { case AMDGPU::FCLAMP_SI: {
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
MI->getOperand(0).getReg()) DebugLoc DL = MI->getDebugLoc();
.addImm(0) // SRC0 modifiers unsigned DestReg = MI->getOperand(0).getReg();
.addOperand(MI->getOperand(1)) BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
.addImm(0) // SRC1 modifiers .addImm(0) // SRC0 modifiers
.addImm(0) // SRC1 .addOperand(MI->getOperand(1))
.addImm(1) // CLAMP .addImm(0) // SRC1 modifiers
.addImm(0); // OMOD .addImm(0) // SRC1
.addImm(1) // CLAMP
.addImm(0); // OMOD
MI->eraseFromParent(); MI->eraseFromParent();
} }
} }