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https://github.com/c64scene-ar/llvm-6502.git
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Proper support for shifts with register shift value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24559 91177308-0d34-0410-b5e6-96231b3b80d8
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c121e33e35
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@ -134,10 +134,11 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode &AM) {
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MatchAddress(N, AM);
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if (AM.BaseType == X86ISelAddressMode::RegBase && !AM.Base.Reg.Val) {
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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} else {
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val)
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AM.Base.Reg = Select(AM.Base.Reg);
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (!AM.IndexReg.Val) {
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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@ -277,10 +278,8 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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default: break;
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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if (N->getOpcode() == ISD::SHL && CN->getValue() == 1) {
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if (CN->getValue() == 1) {
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// X = SHL Y, 1 -> X = ADD Y, Y
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switch (OpVT) {
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default: assert(0 && "Cannot shift this type!");
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@ -291,34 +290,6 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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SDOperand Tmp0 = Select(N->getOperand(0));
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
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}
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} else {
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static const unsigned SHLTab[] = {
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X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL
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};
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static const unsigned SRLTab[] = {
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X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL
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};
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static const unsigned SRATab[] = {
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X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL
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};
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switch (OpVT) {
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default: assert(0 && "Cannot shift this type!");
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case MVT::i1:
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case MVT::i8: Opc = 0; break;
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case MVT::i16: Opc = 1; break;
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case MVT::i32: Opc = 2; break;
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}
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switch (N->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::SHL: Opc = SHLTab[Opc]; break;
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case ISD::SRL: Opc = SRLTab[Opc]; break;
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case ISD::SRA: Opc = SRATab[Opc]; break;
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}
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SDOperand Tmp0 = Select(N->getOperand(0));
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
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}
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break;
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@ -892,11 +892,14 @@ let isTwoAddress = 0 in {
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// Shift instructions
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// FIXME: provide shorter instructions when imm8 == 1
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def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
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"shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shl{b} {%cl, $dst|$dst, %CL}",
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[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
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def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
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"shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
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"shl{w} {%cl, $dst|$dst, %CL}",
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[(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
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def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
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"shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shl{l} {%cl, $dst|$dst, %CL}",
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[(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>;
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def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"shl{b} {$src2, $dst|$dst, $src2}",
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@ -926,11 +929,14 @@ let isTwoAddress = 0 in {
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}
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def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
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"shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shr{b} {%cl, $dst|$dst, %CL}",
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[(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>;
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def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
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"shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
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"shr{w} {%cl, $dst|$dst, %CL}",
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[(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
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def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
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"shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shr{l} {%cl, $dst|$dst, %CL}",
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[(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>;
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def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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"shr{b} {$src2, $dst|$dst, $src2}",
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@ -958,11 +964,14 @@ let isTwoAddress = 0 in {
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}
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def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
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"sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"sar{b} {%cl, $dst|$dst, %CL}",
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[(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>;
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def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
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"sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
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"sar{w} {%cl, $dst|$dst, %CL}",
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[(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
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def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
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"sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"sar{l} {%cl, $dst|$dst, %CL}",
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[(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>;
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def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
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"sar{b} {$src2, $dst|$dst, $src2}",
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