diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 1a48d9cf20e..84dc92e246d 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -760,7 +760,7 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
       RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
       OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
 #else
-      // Default to using register g2 for holding large offsets
+      // Default to using register g4 for holding large offsets
       OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
                                 SparcIntRegClass::g4);
 #endif
@@ -845,7 +845,7 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
       RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
       OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
 #else
-      // Default to using register g2 for holding large offsets
+      // Default to using register g4 for holding large offsets
       OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
                                 SparcIntRegClass::g4);
 #endif
diff --git a/lib/Target/SparcV9/SparcV9_Reg.td b/lib/Target/SparcV9/SparcV9_Reg.td
index 40aaac4abe0..6d5ad1d55a0 100644
--- a/lib/Target/SparcV9/SparcV9_Reg.td
+++ b/lib/Target/SparcV9/SparcV9_Reg.td
@@ -32,7 +32,7 @@ let Namespace = "SparcV9" in {
 
 // For fun, specify a register class.
 //
-// FIXME: the register order should be defined in terms of the prefered
+// FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
 def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,