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Simplify instinfo, set random bits on more fp insts, and fix 1 opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24014 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -196,13 +196,14 @@ class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
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let Inst{4-0} = Fc;
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}
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class FPFormCM<bits<6> opcode, bits<11> fun, dag OL, string asmstr>
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: InstAlpha<opcode, OL, asmstr> {
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class FPFormCM<bits<6> opcode, bits<11> fun, string asmstr>
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: InstAlpha<opcode, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), asmstr> {
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bits<5> Fc;
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bits<5> Fa;
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bits<5> Fb;
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bits<11> Function = fun;
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let isTwoAddress = 1;
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let Inst{25-21} = Fa;
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let Inst{20-16} = Fb;
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let Inst{15-5} = Function;
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@ -136,21 +136,14 @@ def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND
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def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
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def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
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let isTwoAddress = 1 in {
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//conditional moves, fp
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def FCMOVEQ : FPFormCM<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
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def FCMOVGE : FPFormCM<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
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def FCMOVGT : FPFormCM<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
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def FCMOVLE : FPFormCM<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
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def FCMOVLT : FPFormCM<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
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def FCMOVNE : FPFormCM<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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}
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def FCMOVEQ : FPFormCM<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
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def FCMOVGE : FPFormCM<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
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def FCMOVGT : FPFormCM<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
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def FCMOVLE : FPFormCM<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
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def FCMOVLT : FPFormCM<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
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def FCMOVNE : FPFormCM<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
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[(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
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@ -329,10 +322,10 @@ def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC", []>; //Compare unsigned
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def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC", []>; //Compare unsigned quadword less than
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//Comparison, FP
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def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
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def CMPTLE : FPForm<0x16, 0x0A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal
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def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than
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def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
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def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
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def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal
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def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than
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def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
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//There are in the Multimedia extentions, so let's not use them yet
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//def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
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@ -486,11 +479,11 @@ def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC">; //Integer to floating move, T_
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//CVTLQ F-P 17.010 Convert longword to quadword
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//CVTQL F-P 17.030 Convert quadword to longword
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//These use SW completion, may not have function code for that set right (matters for JIT)
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def CVTQS : FPForm<0x16, 0x0BC, "cvtqs $RB,$RC">; //Convert quadword to S_floating
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def CVTQT : FPForm<0x16, 0x0BE, "cvtqt $RB,$RC">; //Convert quadword to T_floating
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def CVTST : FPForm<0x16, 0x2AC, "cvtsts $RB,$RC">; //Convert S_floating to T_floating
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def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC">; //Convert quadword to S_floating
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def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC">; //Convert quadword to T_floating
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def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC">; //Convert S_floating to T_floating
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def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC">; //Convert T_floating to quadword
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def CVTTS : FPForm<0x16, 0x5AC, "cvtts/su $RB,$RC">; //Convert T_floating to S_floating
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def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC">; //Convert T_floating to S_floating
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//S_floating : IEEE Single
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//T_floating : IEEE Double
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