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https://github.com/c64scene-ar/llvm-6502.git
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Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45673 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -709,8 +709,8 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
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FoldOps.push_back(OpIdx);
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FoldOps.push_back(OpIdx);
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}
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}
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MachineInstr *fmi = isSS ? mri_->foldMemoryOperand(MI, FoldOps, Slot)
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MachineInstr *fmi = isSS ? tii_->foldMemoryOperand(MI, FoldOps, Slot)
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: mri_->foldMemoryOperand(MI, FoldOps, DefMI);
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: tii_->foldMemoryOperand(MI, FoldOps, DefMI);
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if (fmi) {
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if (fmi) {
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// Attempt to fold the memory reference into the instruction. If
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// Attempt to fold the memory reference into the instruction. If
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// we can do this, we don't need to insert spill code.
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// we can do this, we don't need to insert spill code.
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@ -746,7 +746,7 @@ bool LiveIntervals::canFoldMemoryOperand(MachineInstr *MI,
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FoldOps.push_back(OpIdx);
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FoldOps.push_back(OpIdx);
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}
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}
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return mri_->canFoldMemoryOperand(MI, FoldOps);
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return tii_->canFoldMemoryOperand(MI, FoldOps);
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}
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}
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bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
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bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
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@ -505,6 +505,7 @@ unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
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MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum) {
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unsigned OpNum) {
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unsigned VirtReg = MI->getOperand(OpNum).getReg();
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unsigned VirtReg = MI->getOperand(OpNum).getReg();
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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// If the virtual register is already available in a physical register,
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// If the virtual register is already available in a physical register,
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// just update the instruction and return.
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// just update the instruction and return.
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@ -525,7 +526,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
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// try to fold the spill into the instruction
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// try to fold the spill into the instruction
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SmallVector<unsigned, 2> Ops;
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SmallVector<unsigned, 2> Ops;
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Ops.push_back(OpNum);
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Ops.push_back(OpNum);
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if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) {
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if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
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++NumFolded;
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++NumFolded;
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// Since we changed the address of MI, make sure to update live variables
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// Since we changed the address of MI, make sure to update live variables
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// to know that the new instruction has the properties of the old one.
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// to know that the new instruction has the properties of the old one.
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@ -545,7 +546,6 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
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<< RegInfo->getName(PhysReg) << "\n";
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<< RegInfo->getName(PhysReg) << "\n";
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// Add move instruction(s)
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// Add move instruction(s)
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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++NumLoads; // Update statistics
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++NumLoads; // Update statistics
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@ -50,6 +50,7 @@ namespace {
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const TargetMachine *TM;
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const TargetMachine *TM;
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MachineFunction *MF;
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MachineFunction *MF;
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const MRegisterInfo *MRI;
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const MRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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LiveVariables *LV;
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LiveVariables *LV;
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// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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@ -478,7 +479,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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// If we can fold this spill into this instruction, do so now.
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// If we can fold this spill into this instruction, do so now.
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SmallVector<unsigned, 2> Ops;
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SmallVector<unsigned, 2> Ops;
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Ops.push_back(OpNum);
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Ops.push_back(OpNum);
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if (MachineInstr* FMI = MRI->foldMemoryOperand(MI, Ops, FrameIndex)) {
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if (MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
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++NumFolded;
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++NumFolded;
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// Since we changed the address of MI, make sure to update live variables
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// Since we changed the address of MI, make sure to update live variables
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// to know that the new instruction has the properties of the old one.
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// to know that the new instruction has the properties of the old one.
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@ -801,6 +802,7 @@ bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
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MF = &Fn;
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MF = &Fn;
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TM = &Fn.getTarget();
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TM = &Fn.getTarget();
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MRI = TM->getRegisterInfo();
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MRI = TM->getRegisterInfo();
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TII = TM->getInstrInfo();
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LV = &getAnalysis<LiveVariables>();
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LV = &getAnalysis<LiveVariables>();
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PhysRegsUsed.assign(MRI->getNumRegs(), -1);
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PhysRegsUsed.assign(MRI->getNumRegs(), -1);
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@ -413,7 +413,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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if (TryUnfold) {
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if (TryUnfold) {
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SmallVector<SDNode*, 4> NewNodes;
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SmallVector<SDNode*, 4> NewNodes;
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if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes))
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if (!TII->unfoldMemoryOperand(DAG, N, NewNodes))
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return NULL;
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return NULL;
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DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
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DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
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@ -793,7 +793,7 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
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DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
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continue;
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continue;
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UnfoldPR = PhysReg;
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UnfoldPR = PhysReg;
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UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
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UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
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false, true);
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false, true);
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}
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}
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}
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}
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@ -831,7 +831,7 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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// unfolded. This allows us to perform the store unfolding
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// unfolded. This allows us to perform the store unfolding
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// optimization.
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// optimization.
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SmallVector<MachineInstr*, 4> NewMIs;
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SmallVector<MachineInstr*, 4> NewMIs;
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if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
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if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
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assert(NewMIs.size() == 1);
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assert(NewMIs.size() == 1);
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MachineInstr *NewMI = NewMIs.back();
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MachineInstr *NewMI = NewMIs.back();
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NewMIs.clear();
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NewMIs.clear();
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@ -839,7 +839,7 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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assert(Idx != -1);
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assert(Idx != -1);
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SmallVector<unsigned, 2> Ops;
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SmallVector<unsigned, 2> Ops;
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Ops.push_back(Idx);
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Ops.push_back(Idx);
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MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS);
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MachineInstr *FoldedMI = TII->foldMemoryOperand(NewMI, Ops, SS);
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if (FoldedMI) {
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if (FoldedMI) {
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if (!VRM.hasPhys(UnfoldVR))
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if (!VRM.hasPhys(UnfoldVR))
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VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
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VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
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@ -1294,7 +1294,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
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unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
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SmallVector<MachineInstr*, 4> NewMIs;
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SmallVector<MachineInstr*, 4> NewMIs;
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if (PhysReg &&
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if (PhysReg &&
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MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
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TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
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MBB.insert(MII, NewMIs[0]);
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MBB.insert(MII, NewMIs[0]);
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VRM.RemoveMachineInstrFromMaps(&MI);
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VRM.RemoveMachineInstrFromMaps(&MI);
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MBB.erase(&MI);
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MBB.erase(&MI);
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@ -1321,7 +1321,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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if (PhysReg &&
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if (PhysReg &&
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!TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
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!TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
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DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
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DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
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MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
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TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
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MBB.insert(MII, NewMIs[0]);
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MBB.insert(MII, NewMIs[0]);
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NewStore = NewMIs[1];
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NewStore = NewMIs[1];
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MBB.insert(MII, NewStore);
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MBB.insert(MII, NewStore);
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