diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e414fdfa7ab..71afb27d304 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3452,7 +3452,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
       TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
     LoadSDNode *LD = cast<LoadSDNode>(LD1);
     unsigned Align = LD->getAlignment();
-    unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
+    unsigned NewAlign = TLI.getTargetData()->
       getABITypeAlignment(VT.getTypeForMVT());
     if (NewAlign <= Align &&
         (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT)))
@@ -3507,7 +3507,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
       !cast<LoadSDNode>(N0)->isVolatile() &&
       (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    unsigned Align = TLI.getTargetMachine().getTargetData()->
+    unsigned Align = TLI.getTargetData()->
       getABITypeAlignment(VT.getTypeForMVT());
     unsigned OrigAlign = LN0->getAlignment();
     if (Align <= OrigAlign) {
@@ -4611,7 +4611,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
       ST->isUnindexed()) {
     unsigned Align = ST->getAlignment();
     MVT SVT = Value.getOperand(0).getValueType();
-    unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
+    unsigned OrigAlign = TLI.getTargetData()->
       getABITypeAlignment(SVT.getTypeForMVT());
     if (Align <= OrigAlign &&
         ((!AfterLegalize && !ST->isVolatile()) ||
@@ -4842,7 +4842,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
     if (NewLoad) {
       // Check the resultant load doesn't need a higher alignment than the
       // original load.
-      unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
+      unsigned NewAlign = TLI.getTargetData()->
         getABITypeAlignment(LVT.getTypeForMVT());
       if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
         return SDValue();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1bada5eea2e..3626081c73f 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -302,7 +302,7 @@ ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
 }
 
 const TargetMachine &SelectionDAG::getTarget() const {
-  return TLI.getTargetMachine();
+  return MF->getTarget();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index e962368a0fd..8a114f74afa 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -310,7 +310,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
         MVT VT = ValueVTs[vti];
         unsigned NumRegisters = TLI.getNumRegisters(VT);
-        const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
+        const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
         for (unsigned i = 0; i != NumRegisters; ++i)
           BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
         PHIReg += NumRegisters;
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 9bf7c994d47..ec7e754bb99 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -327,7 +327,7 @@ public:
   /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
   /// this target when scheduling the DAG.
   virtual HazardRecognizer *CreateTargetHazardRecognizer() {
-    const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
+    const TargetInstrInfo *II = TM.getInstrInfo();
     assert(II && "No InstrInfo?");
     return new SPUHazardRecognizer(*II); 
   }
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index d0dc5b01a73..e90867ced02 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -187,7 +187,7 @@ namespace {
     virtual HazardRecognizer *CreateTargetHazardRecognizer() {
       // Should use subtarget info to pick the right hazard recognizer.  For
       // now, always return a PPC970 recognizer.
-      const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
+      const TargetInstrInfo *II = TM.getInstrInfo();
       assert(II && "No InstrInfo?");
       return new PPCHazardRecognizer970(*II); 
     }