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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
Teach X86FastISel to use AVX versions of instructions when possible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139062 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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1aab5515f6
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@ -198,8 +198,8 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
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RC = X86::GR64RegisterClass;
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RC = X86::GR64RegisterClass;
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break;
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break;
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case MVT::f32:
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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if (X86ScalarSSEf32) {
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Opc = X86::MOVSSrm;
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Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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RC = X86::FR32RegisterClass;
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} else {
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} else {
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Opc = X86::LD_Fp32m;
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Opc = X86::LD_Fp32m;
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@ -207,8 +207,8 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
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}
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}
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break;
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break;
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case MVT::f64:
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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if (X86ScalarSSEf64) {
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Opc = X86::MOVSDrm;
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Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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RC = X86::FR64RegisterClass;
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} else {
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} else {
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Opc = X86::LD_Fp64m;
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Opc = X86::LD_Fp64m;
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@ -250,10 +250,12 @@ X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) {
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case MVT::i32: Opc = X86::MOV32mr; break;
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case MVT::i32: Opc = X86::MOV32mr; break;
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case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
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case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
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case MVT::f32:
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case MVT::f32:
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Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
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Opc = X86ScalarSSEf32 ?
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(Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
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break;
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break;
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case MVT::f64:
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case MVT::f64:
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Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
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Opc = X86ScalarSSEf64 ?
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(Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
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break;
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break;
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}
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}
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@ -805,14 +807,20 @@ bool X86FastISel::X86SelectLoad(const Instruction *I) {
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}
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}
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static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
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static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
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bool HasAVX = Subtarget->hasAVX();
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bool X86ScalarSSEf32 = HasAVX || Subtarget->hasSSE1();
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bool X86ScalarSSEf64 = HasAVX || Subtarget->hasSSE2();
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switch (VT.getSimpleVT().SimpleTy) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: return 0;
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default: return 0;
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case MVT::i8: return X86::CMP8rr;
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case MVT::i8: return X86::CMP8rr;
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case MVT::i16: return X86::CMP16rr;
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case MVT::i16: return X86::CMP16rr;
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case MVT::i32: return X86::CMP32rr;
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case MVT::i32: return X86::CMP32rr;
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case MVT::i64: return X86::CMP64rr;
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case MVT::i64: return X86::CMP64rr;
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case MVT::f32: return Subtarget->hasSSE1() ? X86::UCOMISSrr : 0;
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case MVT::f32:
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case MVT::f64: return Subtarget->hasSSE2() ? X86::UCOMISDrr : 0;
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return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
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case MVT::f64:
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return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
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}
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}
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}
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}
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@ -1215,7 +1223,7 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) {
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bool X86FastISel::X86SelectFPExt(const Instruction *I) {
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bool X86FastISel::X86SelectFPExt(const Instruction *I) {
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// fpext from float to double.
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// fpext from float to double.
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if (Subtarget->hasSSE2() &&
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if (X86ScalarSSEf64 &&
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I->getType()->isDoubleTy()) {
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I->getType()->isDoubleTy()) {
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const Value *V = I->getOperand(0);
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const Value *V = I->getOperand(0);
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if (V->getType()->isFloatTy()) {
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if (V->getType()->isFloatTy()) {
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@ -1234,7 +1242,7 @@ bool X86FastISel::X86SelectFPExt(const Instruction *I) {
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}
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}
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bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
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bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
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if (Subtarget->hasSSE2()) {
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if (X86ScalarSSEf64) {
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if (I->getType()->isFloatTy()) {
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if (I->getType()->isFloatTy()) {
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const Value *V = I->getOperand(0);
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const Value *V = I->getOperand(0);
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if (V->getType()->isDoubleTy()) {
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if (V->getType()->isDoubleTy()) {
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@ -1976,8 +1984,8 @@ unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
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RC = X86::GR64RegisterClass;
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RC = X86::GR64RegisterClass;
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break;
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break;
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case MVT::f32:
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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if (X86ScalarSSEf32) {
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Opc = X86::MOVSSrm;
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Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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RC = X86::FR32RegisterClass;
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} else {
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} else {
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Opc = X86::LD_Fp32m;
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Opc = X86::LD_Fp32m;
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@ -1985,8 +1993,8 @@ unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
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}
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}
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break;
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break;
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case MVT::f64:
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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if (X86ScalarSSEf64) {
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Opc = X86::MOVSDrm;
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Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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RC = X86::FR64RegisterClass;
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} else {
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} else {
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Opc = X86::LD_Fp64m;
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Opc = X86::LD_Fp64m;
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@ -2081,8 +2089,8 @@ unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
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switch (VT.SimpleTy) {
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switch (VT.SimpleTy) {
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default: return false;
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default: return false;
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case MVT::f32:
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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if (X86ScalarSSEf32) {
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Opc = X86::FsFLD0SS;
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Opc = Subtarget->hasAVX() ? X86::VFsFLD0SS : X86::FsFLD0SS;
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RC = X86::FR32RegisterClass;
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RC = X86::FR32RegisterClass;
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} else {
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} else {
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Opc = X86::LD_Fp032;
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Opc = X86::LD_Fp032;
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@ -2090,8 +2098,8 @@ unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
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}
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}
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break;
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break;
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case MVT::f64:
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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if (X86ScalarSSEf64) {
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Opc = X86::FsFLD0SD;
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Opc = Subtarget->hasAVX() ? X86::VFsFLD0SD : X86::FsFLD0SD;
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RC = X86::FR64RegisterClass;
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RC = X86::FR64RegisterClass;
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} else {
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} else {
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Opc = X86::LD_Fp064;
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Opc = X86::LD_Fp064;
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