From 6467dfa40dc6a64fc2d2ca32279727d4accb1bf8 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sat, 12 Nov 2005 19:06:28 +0000 Subject: [PATCH] fix more regressions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24335 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelPattern.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 0074fd448ea..1e6bab6c3a9 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -369,7 +369,7 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst) //assert(0 && "Setcc On float?\n"); std::cerr << "Setcc on float!\n"; Tmp3 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1); Tmp1 = Tmp3; } if (SetCC->getOperand(1).getValueType() == MVT::f32) @@ -377,7 +377,7 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst) //assert (0 && "Setcc On float?\n"); std::cerr << "Setcc on float!\n"; Tmp3 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2); + BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2); Tmp2 = Tmp3; }