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https://github.com/c64scene-ar/llvm-6502.git
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Add SDNode ordering to inlined asm and VA functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91876 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -159,7 +159,8 @@ namespace {
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/// (if applicable), and includes the number of values added into it.
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void AddInlineAsmOperands(unsigned Code,
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bool HasMatching, unsigned MatchingIdx,
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SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
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SelectionDAG &DAG, unsigned Order,
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std::vector<SDValue> &Ops) const;
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};
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}
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@ -5281,20 +5282,30 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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/// values added into it.
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void RegsForValue::AddInlineAsmOperands(unsigned Code,
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bool HasMatching,unsigned MatchingIdx,
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SelectionDAG &DAG,
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SelectionDAG &DAG, unsigned Order,
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std::vector<SDValue> &Ops) const {
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EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
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assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
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unsigned Flag = Code | (Regs.size() << 3);
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if (HasMatching)
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Flag |= 0x80000000 | (MatchingIdx << 16);
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Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
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SDValue Res = DAG.getTargetConstant(Flag, IntPtrTy);
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Ops.push_back(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), Order);
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for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
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unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
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EVT RegisterVT = RegVTs[Value];
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for (unsigned i = 0; i != NumRegs; ++i) {
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assert(Reg < Regs.size() && "Mismatch in # registers expected");
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Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
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SDValue Res = DAG.getRegister(Regs[Reg++], RegisterVT);
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Ops.push_back(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), Order);
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}
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}
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}
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@ -5509,6 +5520,9 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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RegVT, OpInfo.CallOperand);
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OpInfo.ConstraintVT = RegVT;
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}
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if (DisableScheduling)
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DAG.AssignOrdering(OpInfo.CallOperand.getNode(), SDNodeOrder);
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}
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NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
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@ -5545,6 +5559,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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Regs.push_back(*I);
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}
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}
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OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
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const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
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OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
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@ -5775,12 +5790,18 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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Chain = DAG.getStore(Chain, getCurDebugLoc(),
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OpInfo.CallOperand, StackSlot, NULL, 0);
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OpInfo.CallOperand = StackSlot;
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if (DisableScheduling)
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DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
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}
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// There is no longer a Value* corresponding to this operand.
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OpInfo.CallOperandVal = 0;
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// It is now an indirect operand.
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OpInfo.isIndirect = true;
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if (DisableScheduling)
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DAG.AssignOrdering(OpInfo.CallOperand.getNode(), SDNodeOrder);
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}
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// If this constraint is for a specific register, allocate it before
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@ -5788,8 +5809,8 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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if (OpInfo.ConstraintType == TargetLowering::C_Register)
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GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
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}
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ConstraintInfos.clear();
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ConstraintInfos.clear();
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// Second pass - Loop over all of the operands, assigning virtual or physregs
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// to register class operands.
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@ -5863,7 +5884,8 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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2 /* REGDEF */ ,
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false,
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0,
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DAG, AsmNodeOperands);
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DAG, SDNodeOrder,
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AsmNodeOperands);
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break;
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}
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case InlineAsm::isInput: {
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@ -5913,7 +5935,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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SDNodeOrder, Chain, &Flag);
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
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true, OpInfo.getMatchedOperand(),
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DAG, AsmNodeOperands);
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DAG, SDNodeOrder, AsmNodeOperands);
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break;
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} else {
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assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
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@ -5976,7 +5998,8 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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SDNodeOrder, Chain, &Flag);
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OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
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DAG, AsmNodeOperands);
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DAG, SDNodeOrder,
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AsmNodeOperands);
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break;
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}
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case InlineAsm::isClobber: {
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@ -5984,7 +6007,8 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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// allocator is aware that the physreg got clobbered.
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if (!OpInfo.AssignedRegs.Regs.empty())
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OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
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false, 0, DAG,AsmNodeOperands);
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false, 0, DAG, SDNodeOrder,
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AsmNodeOperands);
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break;
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}
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}
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@ -5999,6 +6023,9 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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&AsmNodeOperands[0], AsmNodeOperands.size());
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Flag = Chain.getValue(1);
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if (DisableScheduling)
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DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
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// If this asm returns a register value, copy the result from that register
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// and set it as the value of the call.
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if (!RetValRegs.Regs.empty()) {
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@ -6027,6 +6054,9 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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}
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assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
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if (DisableScheduling)
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DAG.AssignOrdering(Val.getNode(), SDNodeOrder);
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}
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setValue(CS.getInstruction(), Val);
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@ -6050,22 +6080,34 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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// Emit the non-flagged stores from the physregs.
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SmallVector<SDValue, 8> OutChains;
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for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
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OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
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StoresToEmit[i].first,
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getValue(StoresToEmit[i].second),
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StoresToEmit[i].second, 0));
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for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
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SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
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StoresToEmit[i].first,
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getValue(StoresToEmit[i].second),
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StoresToEmit[i].second, 0);
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OutChains.push_back(Val);
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if (DisableScheduling)
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DAG.AssignOrdering(Val.getNode(), SDNodeOrder);
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}
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if (!OutChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
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&OutChains[0], OutChains.size());
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if (DisableScheduling)
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DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
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DAG.setRoot(Chain);
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}
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void SelectionDAGBuilder::visitVAStart(CallInst &I) {
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DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
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MVT::Other, getRoot(),
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getValue(I.getOperand(1)),
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DAG.getSrcValue(I.getOperand(1))));
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SDValue Res = DAG.getNode(ISD::VASTART, getCurDebugLoc(),
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MVT::Other, getRoot(),
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getValue(I.getOperand(1)),
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DAG.getSrcValue(I.getOperand(1)));
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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}
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void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
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@ -6074,22 +6116,30 @@ void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
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DAG.getSrcValue(I.getOperand(0)));
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setValue(&I, V);
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DAG.setRoot(V.getValue(1));
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if (DisableScheduling)
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DAG.AssignOrdering(V.getNode(), SDNodeOrder);
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}
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void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
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DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
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MVT::Other, getRoot(),
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getValue(I.getOperand(1)),
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DAG.getSrcValue(I.getOperand(1))));
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SDValue Res = DAG.getNode(ISD::VAEND, getCurDebugLoc(),
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MVT::Other, getRoot(),
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getValue(I.getOperand(1)),
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DAG.getSrcValue(I.getOperand(1)));
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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}
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void SelectionDAGBuilder::visitVACopy(CallInst &I) {
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DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
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MVT::Other, getRoot(),
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getValue(I.getOperand(1)),
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getValue(I.getOperand(2)),
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DAG.getSrcValue(I.getOperand(1)),
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DAG.getSrcValue(I.getOperand(2))));
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SDValue Res = DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
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MVT::Other, getRoot(),
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getValue(I.getOperand(1)),
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getValue(I.getOperand(2)),
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DAG.getSrcValue(I.getOperand(1)),
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DAG.getSrcValue(I.getOperand(2)));
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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}
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/// TargetLowering::LowerCallTo - This is the default LowerCallTo
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