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The names of VFP variants of half-to-float conversion instructions were
reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -433,25 +433,25 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
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// Between half-precision and single-precision. For disassembly only.
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// FIXME: Verify encoding after integrated assembler is working.
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def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>;
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def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>;
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def : ARMPat<(f32_to_f16 SPR:$a),
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(i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
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def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>;
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def : ARMPat<(f16_to_f32 GPR:$a),
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(VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
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def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>;
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def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>;
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@ -15,14 +15,14 @@ entry:
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%1 = load i16* @y, align 2
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%2 = tail call float @llvm.convert.from.fp16(i16 %0)
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; CHECK: __gnu_h2f_ieee
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; CHECK-FP16: vcvtb.f16.f32
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; CHECK-FP16: vcvtb.f32.f16
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%3 = tail call float @llvm.convert.from.fp16(i16 %1)
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; CHECK: __gnu_h2f_ieee
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; CHECK-FP16: vcvtb.f16.f32
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; CHECK-FP16: vcvtb.f32.f16
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%4 = fadd float %2, %3
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%5 = tail call i16 @llvm.convert.to.fp16(float %4)
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; CHECK: __gnu_f2h_ieee
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; CHECK-FP16: vcvtb.f32.f16
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; CHECK-FP16: vcvtb.f16.f32
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store i16 %5, i16* @x, align 2
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ret void
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}
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