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https://github.com/c64scene-ar/llvm-6502.git
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Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand the node to a libcall. rdar://9280991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129633 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
86837e8745
commit
65279cb9bd
@ -158,7 +158,7 @@ private:
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RTLIB::Libcall Call_I32,
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RTLIB::Libcall Call_I64,
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RTLIB::Libcall Call_I128);
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SDValue ExpandDivRemLibCall(SDNode *Node, bool isSigned, bool isDIV);
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void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
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SDValue ExpandBUILD_VECTOR(SDNode *Node);
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@ -2121,10 +2121,9 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
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return ExpandLibCall(LC, Node, isSigned);
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}
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/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
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/// pairs.
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SDValue SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, bool isSigned,
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bool isDIV) {
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/// isDivRemLibcallAvailable - Return true if divmod libcall is available.
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static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
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const TargetLowering &TLI) {
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RTLIB::Libcall LC;
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switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
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default: assert(0 && "Unexpected request for libcall!");
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@ -2135,17 +2134,18 @@ SDValue SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, bool isSigned,
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case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
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}
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if (!TLI.getLibcallName(LC))
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return SDValue();
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return TLI.getLibcallName(LC) != 0;
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}
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// Only issue divrem libcall if both quotient and remainder are needed.
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/// UseDivRem - Only issue divrem libcall if both quotient and remainder are
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/// needed.
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static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
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unsigned OtherOpcode = 0;
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if (isSigned) {
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if (isSigned)
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OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
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} else {
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else
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OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
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}
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SDNode *OtherNode = 0;
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SDValue Op0 = Node->getOperand(0);
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SDValue Op1 = Node->getOperand(1);
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for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
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@ -2155,32 +2155,28 @@ SDValue SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, bool isSigned,
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continue;
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if (User->getOpcode() == OtherOpcode &&
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User->getOperand(0) == Op0 &&
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User->getOperand(1) == Op1) {
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OtherNode = User;
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break;
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}
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User->getOperand(1) == Op1)
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return true;
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}
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if (!OtherNode)
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return SDValue();
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return false;
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}
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// If the libcall is already generated, no need to issue it again.
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DenseMap<SDValue, SDValue>::iterator I
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= LegalizedNodes.find(SDValue(OtherNode,0));
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if (I != LegalizedNodes.end()) {
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OtherNode = I->second.getNode();
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SDNode *Chain = OtherNode->getOperand(0).getNode();
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for (SDNode::use_iterator UI = Chain->use_begin(), UE = Chain->use_end();
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UI != UE; ++UI) {
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SDNode *User = *UI;
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if (User == OtherNode)
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continue;
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if (isDIV) {
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assert(User->getOpcode() == ISD::CopyFromReg);
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} else {
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assert(User->getOpcode() == ISD::LOAD);
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}
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return SDValue(User, 0);
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}
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/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
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/// pairs.
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void
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SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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unsigned Opcode = Node->getOpcode();
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bool isSigned = Opcode == ISD::SDIVREM;
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RTLIB::Libcall LC;
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switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
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default: assert(0 && "Unexpected request for libcall!");
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case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
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case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
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case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
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case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
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case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
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}
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// The input chain to this libcall is the entry node of the function.
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@ -2228,7 +2224,8 @@ SDValue SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, bool isSigned,
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// Remainder is loaded back from the stack frame.
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SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
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MachinePointerInfo(), false, false, 0);
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return isDIV ? CallInfo.first : Rem;
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Results.push_back(CallInfo.first);
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Results.push_back(Rem);
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}
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/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
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@ -3204,28 +3201,25 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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Tmp2 = Node->getOperand(0);
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Tmp3 = Node->getOperand(1);
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
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(isDivRemLibcallAvailable(Node, isSigned, TLI) &&
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UseDivRem(Node, isSigned, false))) {
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
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} else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
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// X % Y -> X-X/Y*Y
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Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
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Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
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} else if (isSigned) {
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Tmp1 = ExpandDivRemLibCall(Node, true, false);
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if (!Tmp1.getNode())
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Tmp1 = ExpandIntLibCall(Node, true,
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RTLIB::SREM_I8,
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RTLIB::SREM_I16, RTLIB::SREM_I32,
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RTLIB::SREM_I64, RTLIB::SREM_I128);
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} else {
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Tmp1 = ExpandDivRemLibCall(Node, false, false);
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if (!Tmp1.getNode())
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Tmp1 = ExpandIntLibCall(Node, false,
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RTLIB::UREM_I8,
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RTLIB::UREM_I16, RTLIB::UREM_I32,
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RTLIB::UREM_I64, RTLIB::UREM_I128);
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}
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} else if (isSigned)
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Tmp1 = ExpandIntLibCall(Node, true,
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RTLIB::SREM_I8,
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RTLIB::SREM_I16, RTLIB::SREM_I32,
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RTLIB::SREM_I64, RTLIB::SREM_I128);
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else
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Tmp1 = ExpandIntLibCall(Node, false,
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RTLIB::UREM_I8,
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RTLIB::UREM_I16, RTLIB::UREM_I32,
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RTLIB::UREM_I64, RTLIB::UREM_I128);
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Results.push_back(Tmp1);
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break;
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}
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@ -3235,26 +3229,21 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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EVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
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(isDivRemLibcallAvailable(Node, isSigned, TLI) &&
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UseDivRem(Node, isSigned, true)))
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
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Node->getOperand(1));
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else if (isSigned) {
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Tmp1 = ExpandDivRemLibCall(Node, true, true);
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if (!Tmp1.getNode()) {
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Tmp1 = ExpandIntLibCall(Node, true,
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RTLIB::SDIV_I8,
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RTLIB::SDIV_I16, RTLIB::SDIV_I32,
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RTLIB::SDIV_I64, RTLIB::SDIV_I128);
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}
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} else {
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Tmp1 = ExpandDivRemLibCall(Node, false, true);
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if (!Tmp1.getNode()) {
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Tmp1 = ExpandIntLibCall(Node, false,
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RTLIB::UDIV_I8,
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RTLIB::UDIV_I16, RTLIB::UDIV_I32,
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RTLIB::UDIV_I64, RTLIB::UDIV_I128);
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}
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}
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else if (isSigned)
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Tmp1 = ExpandIntLibCall(Node, true,
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RTLIB::SDIV_I8,
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RTLIB::SDIV_I16, RTLIB::SDIV_I32,
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RTLIB::SDIV_I64, RTLIB::SDIV_I128);
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else
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Tmp1 = ExpandIntLibCall(Node, false,
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RTLIB::UDIV_I8,
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RTLIB::UDIV_I16, RTLIB::UDIV_I32,
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RTLIB::UDIV_I64, RTLIB::UDIV_I128);
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Results.push_back(Tmp1);
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break;
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}
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@ -3271,6 +3260,11 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(Tmp1.getValue(1));
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break;
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}
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case ISD::SDIVREM:
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case ISD::UDIVREM:
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// Expand into divrem libcall
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ExpandDivRemLibCall(Node, Results);
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break;
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case ISD::MUL: {
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EVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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@ -25,3 +25,34 @@ entry:
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store i32 %rem, i32* %arrayidx6, align 4
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ret void
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}
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; rdar://9280991
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@flags = external unnamed_addr global i32
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@tabsize = external unnamed_addr global i32
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define void @do_indent(i32 %cols) nounwind {
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entry:
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; CHECK: do_indent:
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%0 = load i32* @flags, align 4
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%1 = and i32 %0, 67108864
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %bb1, label %bb
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bb:
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; CHECK: bl ___divmodsi4
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%3 = load i32* @tabsize, align 4
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%4 = srem i32 %cols, %3
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%5 = sdiv i32 %cols, %3
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%6 = tail call i32 @llvm.objectsize.i32(i8* null, i1 false)
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%7 = tail call i8* @__memset_chk(i8* null, i32 9, i32 %5, i32 %6) nounwind
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br label %bb1
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bb1:
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%line_indent_len.0 = phi i32 [ %4, %bb ], [ 0, %entry ]
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%8 = getelementptr inbounds i8* null, i32 %line_indent_len.0
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store i8 0, i8* %8, align 1
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ret void
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}
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declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readnone
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declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
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