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Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed

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INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-03-31 21:55:24 +00:00
parent b83169195c
commit 653159f4aa
3 changed files with 12 additions and 6 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
View File

@ -2685,7 +2685,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, Op.getOperand(0), N1, N2);
return DAG.getNode(X86ISD::PINSRW, VT, Op.getOperand(0), N1, N2);
}
return SDOperand();
@ -2726,6 +2726,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::S2VEC: return "X86ISD::S2VEC";
case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
case X86ISD::PINSRW: return "X86ISD::PINSRW";
}
}

6
lib/Target/X86/X86ISelLowering.h
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@ -155,8 +155,12 @@ namespace llvm {
ZEXT_S2VEC,
/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
/// i32, corresponds to X86::PINSRW.
/// i32, corresponds to X86::PEXTRW.
PEXTRW,
/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
/// corresponds to X86::PINSRW.
PINSRW,
};
// X86 specific condition code. These correspond to X86_*_COND in

9
lib/Target/X86/X86InstrSSE.td
View File

@ -27,9 +27,10 @@ def X86s2vec : SDNode<"X86ISD::S2VEC",
SDTypeProfile<1, 1, []>, []>;
def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
SDTypeProfile<1, 1, []>, []>;
def X86pextrw : SDNode<"X86ISD::PEXTRW",
SDTypeProfile<1, 2, []>, []>;
def X86pinsrw : SDNode<"X86ISD::PINSRW",
SDTypeProfile<1, 3, []>, []>;
//===----------------------------------------------------------------------===//
// SSE pattern fragments
@ -1468,13 +1469,13 @@ let isTwoAddress = 1 in {
def PINSRWrr : PDIi8<0xC4, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst, (v8i16 (vector_insert (v8i16 VR128:$src1),
R32:$src2, (i32 imm:$src3))))]>;
[(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
R32:$src2, (i32 imm:$src3))))]>;
def PINSRWrm : PDIi8<0xC4, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(v8i16 (vector_insert (v8i16 VR128:$src1),
(v8i16 (X86pinsrw (v8i16 VR128:$src1),
(i32 (anyext (loadi16 addr:$src2))),
(i32 imm:$src3))))]>;
}