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X86_COND_C and X86_COND_NC are alternate mnemonics for

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X86_COND_B and X86_COND_AE, respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-01-07 00:15:08 +00:00
parent bc03979536
commit 653456c351
7 changed files with 32 additions and 69 deletions
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14
lib/Target/X86/X86FastISel.cpp
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@ -758,11 +758,11 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
// %obit = extractvalue { i32, i1 } %t, 1
// br i1 %obit, label %overflow, label %normal
//
// The %sum and %obit are converted in an ADD and a SETO/SETC before
// The %sum and %obit are converted in an ADD and a SETO/SETB before
// reaching the branch. Therefore, we search backwards through the MBB
// looking for the SETO/SETC instruction. If an instruction modifies the
// EFLAGS register before we reach the SETO/SETC instruction, then we can't
// convert the branch into a JO/JC instruction.
// looking for the SETO/SETB instruction. If an instruction modifies the
// EFLAGS register before we reach the SETO/SETB instruction, then we can't
// convert the branch into a JO/JB instruction.
Value *Agg = EI->getAggregateOperand();
@ -814,9 +814,9 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
if (SetMI) {
unsigned OpCode = SetMI->getOpcode();
if (OpCode == X86::SETOr || OpCode == X86::SETCr) {
if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
BuildMI(MBB, TII.get((OpCode == X86::SETOr) ?
X86::JO : X86::JC)).addMBB(TrueMBB);
X86::JO : X86::JB)).addMBB(TrueMBB);
FastEmitBranch(FalseMBB);
MBB->addSuccessor(TrueMBB);
return true;
@ -1086,7 +1086,7 @@ bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
X86::SETOr : X86::SETCr), ResultReg);
X86::SETOr : X86::SETBr), ResultReg);
return true;
}
}

10
lib/Target/X86/X86ISelLowering.cpp
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@ -5057,7 +5057,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
unsigned Cond = CC == ISD::SETEQ ? X86::COND_NC : X86::COND_C;
unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
return DAG.getNode(X86ISD::SETCC, MVT::i8,
DAG.getConstant(Cond, MVT::i8), BT);
}
@ -5283,7 +5283,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
default: break;
case X86::COND_O:
case X86::COND_C:
case X86::COND_B:
// These can only come from an arithmetic instruction with overflow,
// e.g. SADDO, UADDO.
Cond = Cond.getNode()->getOperand(1);
@ -6243,7 +6243,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
break;
case ISD::UADDO:
BaseOp = X86ISD::ADD;
Cond = X86::COND_C;
Cond = X86::COND_B;
break;
case ISD::SSUBO:
BaseOp = X86ISD::SUB;
@ -6251,7 +6251,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
break;
case ISD::USUBO:
BaseOp = X86ISD::SUB;
Cond = X86::COND_C;
Cond = X86::COND_B;
break;
case ISD::SMULO:
BaseOp = X86ISD::SMUL;
@ -6259,7 +6259,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
break;
case ISD::UMULO:
BaseOp = X86ISD::UMUL;
Cond = X86::COND_C;
Cond = X86::COND_B;
break;
}

8
lib/Target/X86/X86InstrInfo.cpp
View File

@ -282,13 +282,11 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
{ X86::SETAr, X86::SETAm, 0 },
{ X86::SETBEr, X86::SETBEm, 0 },
{ X86::SETBr, X86::SETBm, 0 },
{ X86::SETCr, X86::SETCm, 0 },
{ X86::SETEr, X86::SETEm, 0 },
{ X86::SETGEr, X86::SETGEm, 0 },
{ X86::SETGr, X86::SETGm, 0 },
{ X86::SETLEr, X86::SETLEm, 0 },
{ X86::SETLr, X86::SETLm, 0 },
{ X86::SETNCr, X86::SETNCm, 0 },
{ X86::SETNEr, X86::SETNEm, 0 },
{ X86::SETNOr, X86::SETNOm, 0 },
{ X86::SETNPr, X86::SETNPm, 0 },
@ -1389,8 +1387,6 @@ static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
case X86::JNP: return X86::COND_NP;
case X86::JO: return X86::COND_O;
case X86::JNO: return X86::COND_NO;
case X86::JC: return X86::COND_C;
case X86::JNC: return X86::COND_NC;
}
}
@ -1413,8 +1409,6 @@ unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
case X86::COND_NP: return X86::JNP;
case X86::COND_O: return X86::JO;
case X86::COND_NO: return X86::JNO;
case X86::COND_C: return X86::JC;
case X86::COND_NC: return X86::JNC;
}
}
@ -1439,8 +1433,6 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
case X86::COND_NP: return X86::COND_P;
case X86::COND_O: return X86::COND_NO;
case X86::COND_NO: return X86::COND_O;
case X86::COND_C: return X86::COND_NC;
case X86::COND_NC: return X86::COND_C;
}
}

8
lib/Target/X86/X86InstrInfo.h
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@ -41,11 +41,9 @@ namespace X86 {
COND_NO = 10,
COND_NP = 11,
COND_NS = 12,
COND_NC = 13,
COND_O = 14,
COND_P = 15,
COND_S = 16,
COND_C = 17,
COND_O = 13,
COND_P = 14,
COND_S = 15,
// Artificial condition codes. These are used by AnalyzeBranch
// to indicate a block terminated with two conditional branches to

55
lib/Target/X86/X86InstrInfo.td
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@ -236,24 +236,22 @@ include "X86InstrFormats.td"
// X86 specific condition code. These correspond to CondCode in
// X86InstrInfo.h. They must be kept in synch.
def X86_COND_A : PatLeaf<(i8 0)>;
def X86_COND_AE : PatLeaf<(i8 1)>;
def X86_COND_B : PatLeaf<(i8 2)>;
def X86_COND_BE : PatLeaf<(i8 3)>;
def X86_COND_E : PatLeaf<(i8 4)>;
def X86_COND_G : PatLeaf<(i8 5)>;
def X86_COND_GE : PatLeaf<(i8 6)>;
def X86_COND_L : PatLeaf<(i8 7)>;
def X86_COND_LE : PatLeaf<(i8 8)>;
def X86_COND_NE : PatLeaf<(i8 9)>;
def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
def X86_COND_NO : PatLeaf<(i8 10)>;
def X86_COND_NP : PatLeaf<(i8 11)>;
def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
def X86_COND_NS : PatLeaf<(i8 12)>;
def X86_COND_NC : PatLeaf<(i8 13)>;
def X86_COND_O : PatLeaf<(i8 14)>;
def X86_COND_P : PatLeaf<(i8 15)>;
def X86_COND_S : PatLeaf<(i8 16)>;
def X86_COND_C : PatLeaf<(i8 17)>;
def X86_COND_O : PatLeaf<(i8 13)>;
def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
def X86_COND_S : PatLeaf<(i8 15)>;
def i16immSExt8 : PatLeaf<(i16 imm), [{
// i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
@ -465,10 +463,6 @@ def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
[(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
[(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
def JC : IBr<0x82, (ins brtarget:$dst), "jc\t$dst",
[(X86brcond bb:$dst, X86_COND_C, EFLAGS)]>, TB;
def JNC : IBr<0x83, (ins brtarget:$dst), "jnc\t$dst",
[(X86brcond bb:$dst, X86_COND_NC, EFLAGS)]>, TB;
} // Uses = [EFLAGS]
//===----------------------------------------------------------------------===//
@ -2534,27 +2528,6 @@ def SETNOm : I<0x91, MRM0m,
"setno\t$dst",
[(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
TB; // [mem8] = not overflow
def SETCr : I<0x92, MRM0r,
(outs GR8 :$dst), (ins),
"setc\t$dst",
[(set GR8:$dst, (X86setcc X86_COND_C, EFLAGS))]>,
TB; // GR8 = carry
def SETCm : I<0x92, MRM0m,
(outs), (ins i8mem:$dst),
"setc\t$dst",
[(store (X86setcc X86_COND_C, EFLAGS), addr:$dst)]>,
TB; // [mem8] = carry
def SETNCr : I<0x93, MRM0r,
(outs GR8 :$dst), (ins),
"setnc\t$dst",
[(set GR8:$dst, (X86setcc X86_COND_NC, EFLAGS))]>,
TB; // GR8 = not carry
def SETNCm : I<0x93, MRM0m,
(outs), (ins i8mem:$dst),
"setnc\t$dst",
[(store (X86setcc X86_COND_NC, EFLAGS), addr:$dst)]>,
TB; // [mem8] = not carry
} // Uses = [EFLAGS]

4
test/CodeGen/X86/add-with-overflow.ll
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@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
; RUN: llvm-as < %s | llc -march=x86 | grep {jc} | count 2
; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jc} | count 2
; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"

2
test/CodeGen/X86/sub-with-overflow.ll
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@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 1
; RUN: llvm-as < %s | llc -march=x86 | grep {jc} | count 1
; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 1
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"