mirror of
https://github.com/c64scene-ar/llvm-6502.git
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More SSE refactoring, this time with different types of MOVs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
420ab9102c
commit
6560ed35b4
@ -560,6 +560,131 @@ def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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(MOVSDmr addr:$dst,
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(EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
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// Move Aligned/Unaligned floating point values
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multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
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X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d,
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bit IsReMaterializable = 1> {
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let neverHasSideEffects = 1 in
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), asm, [], d>;
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), asm,
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[(set RC:$dst, (ld_frag addr:$src))], d>;
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}
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defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
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"movaps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
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"movapd\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
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"movups\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
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"movupd\t{$src, $dst|$dst, $src}",
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SSEPackedDouble, 0>, TB, OpSize;
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def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
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def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
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def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(store (v4f32 VR128:$src), addr:$dst)]>;
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def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(store (v2f64 VR128:$src), addr:$dst)]>;
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// Intrinsic forms of MOVUPS/D load and store
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
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def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
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def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
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def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
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// Move Low/High packed floating point values
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multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
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PatFrag mov_frag, string base_opc,
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string asm_opr> {
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def PSrm : PI<opc, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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!strconcat(!strconcat(base_opc,"s"), asm_opr),
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[(set RC:$dst,
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(mov_frag RC:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
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SSEPackedSingle>, TB;
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def PDrm : PI<opc, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f64mem:$src2),
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!strconcat(!strconcat(base_opc,"d"), asm_opr),
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[(set RC:$dst, (v2f64 (mov_frag RC:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))))],
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SSEPackedDouble>, TB, OpSize;
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}
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let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
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defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
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"\t{$src2, $dst|$dst, $src2}">;
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defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
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"\t{$src2, $dst|$dst, $src2}">;
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}
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def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movlps\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
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(iPTR 0))), addr:$dst)]>;
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def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movlpd\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract (v2f64 VR128:$src),
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(iPTR 0))), addr:$dst)]>;
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// v2f64 extract element 1 is always custom lowered to unpack high to low
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// and extract element 0 so the non-store version isn't too horrible.
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def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movhps\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract
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(unpckh (bc_v2f64 (v4f32 VR128:$src)),
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(undef)), (iPTR 0))), addr:$dst)]>;
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def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movhpd\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract
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(v2f64 (unpckh VR128:$src, (undef))),
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(iPTR 0))), addr:$dst)]>;
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let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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"movlhps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
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def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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"movhlps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
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}
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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let AddedComplexity = 20 in {
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def : Pat<(v4f32 (movddup VR128:$src, (undef))),
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(MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
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def : Pat<(v2i64 (movddup VR128:$src, (undef))),
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(MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Conversion Instructions
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//===----------------------------------------------------------------------===//
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@ -1335,101 +1460,6 @@ let isCommutable = 0 in {
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defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
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}
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//===----------------------------------------------------------------------===//
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// SSE packed FP Instructions
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// Move Instructions
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let neverHasSideEffects = 1 in
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def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movaps\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
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def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
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let neverHasSideEffects = 1 in
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def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movups\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (loadv4f32 addr:$src))]>;
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def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(store (v4f32 VR128:$src), addr:$dst)]>;
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// Intrinsic forms of MOVUPS load and store
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
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def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
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let Constraints = "$src1 = $dst" in {
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let AddedComplexity = 20 in {
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def MOVLPSrm : PSI<0x12, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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"movlps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(movlp VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
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def MOVHPSrm : PSI<0x16, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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"movhps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
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} // AddedComplexity
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} // Constraints = "$src1 = $dst"
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movlps\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
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(iPTR 0))), addr:$dst)]>;
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// v2f64 extract element 1 is always custom lowered to unpack high to low
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// and extract element 0 so the non-store version isn't too horrible.
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def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movhps\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract
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(unpckh (bc_v2f64 (v4f32 VR128:$src)),
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(undef)), (iPTR 0))), addr:$dst)]>;
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let Constraints = "$src1 = $dst" in {
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let AddedComplexity = 20 in {
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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"movlhps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
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def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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"movhlps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
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} // AddedComplexity
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} // Constraints = "$src1 = $dst"
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let AddedComplexity = 20 in {
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def : Pat<(v4f32 (movddup VR128:$src, (undef))),
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(MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
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def : Pat<(v2i64 (movddup VR128:$src, (undef))),
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(MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
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}
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// Arithmetic
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/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
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@ -1609,71 +1639,6 @@ def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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//===---------------------------------------------------------------------===//
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// SSE packed FP Instructions
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// Move Instructions
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let neverHasSideEffects = 1 in
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def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movapd\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
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def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
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let neverHasSideEffects = 1 in
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def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movupd\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1 in
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def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (loadv2f64 addr:$src))]>;
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def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(store (v2f64 VR128:$src), addr:$dst)]>;
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// Intrinsic forms of MOVUPD load and store
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def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
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def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
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let Constraints = "$src1 = $dst" in {
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let AddedComplexity = 20 in {
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def MOVLPDrm : PDI<0x12, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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"movlpd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (movlp VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))))]>;
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def MOVHPDrm : PDI<0x16, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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"movhpd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (movlhps VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))))]>;
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} // AddedComplexity
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} // Constraints = "$src1 = $dst"
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def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movlpd\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract (v2f64 VR128:$src),
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(iPTR 0))), addr:$dst)]>;
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// v2f64 extract element 1 is always custom lowered to unpack high to low
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// and extract element 0 so the non-store version isn't too horrible.
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def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
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"movhpd\t{$src, $dst|$dst, $src}",
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[(store (f64 (vector_extract
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(v2f64 (unpckh VR128:$src, (undef))),
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(iPTR 0))), addr:$dst)]>;
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// SSE2 instructions without OpSize prefix
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def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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