From 6571101cb727740951a452d667479cea3f17bc3b Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 19 Nov 2010 22:22:37 +0000 Subject: [PATCH] Fix encoding for ARM MLS instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119855 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 02db6ab0d51..636801b09a2 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2547,14 +2547,16 @@ def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), let Inst{15-12} = Ra; } -def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), - IIC_iMAC32, "mls", "\t$dst, $a, $b, $c", - [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>, +def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), + IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", + [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; bits<4> Rm; bits<4> Rn; + bits<4> Ra; let Inst{19-16} = Rd; + let Inst{15-12} = Ra; let Inst{11-8} = Rm; let Inst{3-0} = Rn; }