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Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in the case that the full register is to be split into subvectors instead of scalars. This replaces uses of VBIT_CONVERT to present values as vector-of-vector types in order to make whole subvectors accessible via BUILD_VECTOR and EXTRACT_VECTOR_ELT. This is in preparation for adding extended ValueType values, where having vector-of-vector types is undesirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37569 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -267,6 +267,19 @@ namespace ISD {
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/// element number IDX.
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EXTRACT_VECTOR_ELT,
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/// VCONCAT_VECTORS(VECTOR0, VECTOR1, ..., COUNT,TYPE) - Given a number of
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/// values of MVT::Vector type with the same length and element type, this
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/// produces a concatenated MVT::Vector result value, with length equal to
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/// the sum of the input vectors. This can only be used before
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/// legalization.
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VCONCAT_VECTORS,
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/// VEXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
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/// MVT::Vector value) starting with the (potentially variable)
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/// element number IDX, which must be a multiple of the result vector
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/// length. This can only be used before legalization.
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VEXTRACT_SUBVECTOR,
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/// VVECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC, COUNT,TYPE) - Returns a vector,
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/// of the same type as VEC1/VEC2. SHUFFLEVEC is a VBUILD_VECTOR of
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/// constant int values that indicate which value each result element will
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@ -225,6 +225,7 @@ private:
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SDOperand &Lo, SDOperand &Hi);
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SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
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SDOperand LowerVEXTRACT_SUBVECTOR(SDOperand Op);
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SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
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SDOperand getIntPtrConstant(uint64_t Val) {
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@ -1178,6 +1179,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
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break;
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case ISD::VEXTRACT_SUBVECTOR:
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Result = LegalizeOp(LowerVEXTRACT_SUBVECTOR(Op));
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break;
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case ISD::CALLSEQ_START: {
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SDNode *CallEnd = FindCallEndFromCallStart(Node);
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@ -3561,6 +3566,9 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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case ISD::VEXTRACT_VECTOR_ELT:
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Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
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break;
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case ISD::VEXTRACT_SUBVECTOR:
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Result = PromoteOp(LowerVEXTRACT_SUBVECTOR(Op));
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break;
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case ISD::EXTRACT_VECTOR_ELT:
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Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
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break;
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@ -3622,6 +3630,37 @@ SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
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}
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}
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/// LowerVEXTRACT_SUBVECTOR - Lower a VEXTRACT_SUBVECTOR operation. For now
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/// we assume the operation can be split if it is not already legal.
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SDOperand SelectionDAGLegalize::LowerVEXTRACT_SUBVECTOR(SDOperand Op) {
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// We know that operand #0 is the Vec vector. For now we assume the index
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// is a constant and that the extracted result is a supported hardware type.
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SDOperand Vec = Op.getOperand(0);
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SDOperand Idx = LegalizeOp(Op.getOperand(1));
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SDNode *InVal = Vec.Val;
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unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
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if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
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// This must be an access of the desired vector length. Return it.
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return PackVectorOp(Vec, Op.getValueType());
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}
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ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
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SDOperand Lo, Hi;
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SplitVectorOp(Vec, Lo, Hi);
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if (CIdx->getValue() < NumElems/2) {
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Vec = Lo;
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} else {
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Vec = Hi;
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Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
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}
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// It's now an extract from the appropriate high or low part. Recurse.
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Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
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return LowerVEXTRACT_SUBVECTOR(Op);
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}
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/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
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/// memory traffic.
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SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
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@ -5501,6 +5540,21 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
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Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
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break;
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}
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case ISD::VCONCAT_VECTORS: {
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unsigned NewNumSubvectors = (Node->getNumOperands() - 2) / 2;
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SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
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Node->op_begin()+NewNumSubvectors);
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LoOps.push_back(NewNumEltsNode);
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LoOps.push_back(TypeNode);
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Lo = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, &LoOps[0], LoOps.size());
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SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
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Node->op_end()-2);
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HiOps.push_back(NewNumEltsNode);
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HiOps.push_back(TypeNode);
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Hi = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, &HiOps[0], HiOps.size());
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break;
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}
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case ISD::VADD:
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case ISD::VSUB:
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case ISD::VMUL:
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@ -5655,6 +5709,11 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
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}
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}
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break;
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case ISD::VCONCAT_VECTORS:
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assert(Node->getOperand(0).getValueType() == NewVT &&
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"Concat of non-legal vectors not yet supported!");
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Result = Node->getOperand(0);
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break;
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case ISD::VINSERT_VECTOR_ELT:
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if (!MVT::isVector(NewVT)) {
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// Returning a scalar? Must be the inserted element.
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@ -5665,6 +5724,10 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
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Node->getOperand(1), Node->getOperand(2));
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}
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break;
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case ISD::VEXTRACT_SUBVECTOR:
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Result = PackVectorOp(Node->getOperand(0), NewVT);
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assert(Result.getValueType() == NewVT);
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break;
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case ISD::VVECTOR_SHUFFLE:
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if (!MVT::isVector(NewVT)) {
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// Returning a scalar? Figure out if it is the LHS or RHS and return it.
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@ -2865,6 +2865,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
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case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
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case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt";
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case ISD::VCONCAT_VECTORS: return "vconcat_vectors";
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case ISD::VEXTRACT_SUBVECTOR: return "vextract_subvector";
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case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
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case ISD::VBUILD_VECTOR: return "vbuild_vector";
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case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
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@ -761,7 +761,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
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unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT,
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PTyLegalElementVT);
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// Build a VBUILD_VECTOR with the input registers.
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// Build a VBUILD_VECTOR or VCONCAT_VECTORS with the input registers.
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SmallVector<SDOperand, 8> Ops;
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if (PTyElementVT == PTyLegalElementVT) {
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// If the value types are legal, just VBUILD the CopyFromReg nodes.
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@ -791,16 +791,15 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
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}
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}
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Ops.push_back(DAG.getConstant(NE, MVT::i32));
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Ops.push_back(DAG.getValueType(PTyElementVT));
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N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
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// Finally, use a VBIT_CONVERT to make this available as the appropriate
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// vector type.
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N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
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DAG.getConstant(PTy->getNumElements(),
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MVT::i32),
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DAG.getValueType(TLI.getValueType(PTy->getElementType())));
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if (MVT::isVector(PTyElementVT)) {
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Ops.push_back(DAG.getConstant(NE * MVT::getVectorNumElements(PTyElementVT), MVT::i32));
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Ops.push_back(DAG.getValueType(MVT::getVectorBaseType(PTyElementVT)));
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N = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, &Ops[0], Ops.size());
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} else {
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Ops.push_back(DAG.getConstant(NE, MVT::i32));
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Ops.push_back(DAG.getValueType(PTyElementVT));
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N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
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}
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}
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return N;
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@ -4426,21 +4425,19 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
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MVT::ValueType PTyElementVT, PTyLegalElementVT;
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unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()),
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PTyElementVT, PTyLegalElementVT);
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uint64_t SrcVL = cast<ConstantSDNode>(*(Op.Val->op_end()-2))->getValue();
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// Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
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// MVT::Vector type.
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Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
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DAG.getConstant(NE, MVT::i32),
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DAG.getValueType(PTyElementVT));
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// Loop over all of the elements of the resultant vector,
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// VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
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// copying them into output registers.
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// VEXTRACT_VECTOR_ELT'ing or VEXTRACT_SUBVECTOR'ing them, converting them
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// to PTyLegalElementVT, then copying them into output registers.
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SmallVector<SDOperand, 8> OutChains;
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SDOperand Root = getRoot();
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for (unsigned i = 0; i != NE; ++i) {
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SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
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Op, DAG.getConstant(i, TLI.getPointerTy()));
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SDOperand Elt = MVT::isVector(PTyElementVT) ?
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DAG.getNode(ISD::VEXTRACT_SUBVECTOR, PTyElementVT,
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Op, DAG.getConstant(i * (SrcVL / NE), TLI.getPointerTy())) :
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DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
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Op, DAG.getConstant(i, TLI.getPointerTy()));
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if (PTyElementVT == PTyLegalElementVT) {
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// Elements are legal.
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OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
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