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Disable formation of rlwinm instructions from SRA bases. This fixes

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the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-09 05:36:17 +00:00
parent 0cb34c4714
commit 65a419a104
1 changed files with 2 additions and 2 deletions
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4
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -217,7 +217,7 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
return false;
}
// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
// isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
// and mask opcode and mask operation.
static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
unsigned &SH, unsigned &MB, unsigned &ME) {
@ -1278,7 +1278,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
}
case ISD::SRA: {
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
if (0 &&isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME))
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
Select(N->getOperand(0).getOperand(0)),