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a bunch of ssse3 instructions are misencoded to think they have an

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i8 field when they really do not.  This fixes rdar://7840289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-04-17 07:38:24 +00:00
parent ca5e4f8e19
commit 65de1b9eb3
2 changed files with 10 additions and 0 deletions
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3
lib/Target/X86/X86InstrSSE.td
View File

@ -2878,6 +2878,7 @@ let Constraints = "$src1 = $dst" in {
}
}
let ImmT = NoImm in { // None of these have i8 immediate fields.
defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
int_x86_ssse3_phadd_w,
int_x86_ssse3_phadd_w_128>;
@ -2902,6 +2903,7 @@ defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
int_x86_ssse3_pmul_hr_sw,
int_x86_ssse3_pmul_hr_sw_128, 1>;
defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
int_x86_ssse3_pshuf_b,
int_x86_ssse3_pshuf_b_128>;
@ -2914,6 +2916,7 @@ defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
int_x86_ssse3_psign_d,
int_x86_ssse3_psign_d_128>;
}
// palignr patterns.
let Constraints = "$src1 = $dst" in {

7
test/MC/AsmParser/X86/x86_32-encoding.s
View File

@ -9961,3 +9961,10 @@
// CHECK: aeskeygenassist $125, (%edx,%eax,4), %xmm2
// CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d]
aeskeygenassist $125, (%edx,%eax,4), %xmm2
// rdar://7840289
// CHECK: pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A]
// CHECK: fixup A - offset: 5, value: CPI1_0-4
pshufb CPI1_0(%rip), %xmm1