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Look at shuffles of build_vectors in DAGCombiner::visitEXTRACT_VECTOR_ELT
When the loop vectorizer vectorizes code that uses the loop induction variable, we often end up with IR like this: %b1 = insertelement <2 x i32> undef, i32 %v, i32 0 %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer %i = add <2 x i32> %b2, <i32 2, i32 3> If the add in this example is not legal (as is the case on PPC with VSX), it will be scalarized, and we'll end up with a number of extract_vector_elt nodes with the vector shuffle as the input operand, and that vector shuffle is fed by one or more build_vector nodes. By the time that vector operations are expanded, visitEXTRACT_VECTOR_ELT will not create new extract_vector_elt by looking through the vector shuffle (to make sure that no illegal operations are created), and so the extract_vector_elt -> vector shuffle -> build_vector is never simplified to an operand of the build vector. By looking at build_vectors through a shuffle we fix this particular situation, preventing a vector from being built, only to be deconstructed again (for the scalarized add) -- an expensive proposition when this all needs to be done via the stack. We probably want a more comprehensive fix here where we look back recursively through any shuffles to any build_vectors or scalar_to_vectors, etc. but that can come later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205179 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9745,9 +9745,10 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// We only perform this optimization before the op legalization phase because
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// we may introduce new vector instructions which are not backed by TD
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// patterns. For example on AVX, extracting elements from a wide vector
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// without using extract_subvector.
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// without using extract_subvector. However, if we can find an underlying
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// scalar value, then we can always use that.
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if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
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&& ConstEltNo && !LegalOperations) {
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&& ConstEltNo) {
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int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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int NumElem = VT.getVectorNumElements();
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
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@ -9759,16 +9760,32 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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return DAG.getUNDEF(NVT);
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// Select the right vector half to extract from.
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SDValue SVInVec;
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if (OrigElt < NumElem) {
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InVec = InVec->getOperand(0);
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SVInVec = InVec->getOperand(0);
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} else {
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InVec = InVec->getOperand(1);
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SVInVec = InVec->getOperand(1);
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OrigElt -= NumElem;
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}
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EVT IndexTy = TLI.getVectorIdxTy();
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
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InVec, DAG.getConstant(OrigElt, IndexTy));
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if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
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SDValue InOp = SVInVec.getOperand(OrigElt);
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if (InOp.getValueType() != NVT) {
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assert(InOp.getValueType().isInteger() && NVT.isInteger());
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InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
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}
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return InOp;
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}
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// FIXME: We should handle recursing on other vector shuffles and
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// scalar_to_vector here as well.
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if (!LegalOperations) {
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EVT IndexTy = TLI.getVectorIdxTy();
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
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SVInVec, DAG.getConstant(OrigElt, IndexTy));
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}
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}
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// Perform only after legalization to ensure build_vector / vector_shuffle
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@ -624,3 +624,19 @@ define <2 x double> @test70(<2 x i8> %a) {
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; CHECK: blr
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}
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define <2 x i32> @test80(i32 %v) {
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%b1 = insertelement <2 x i32> undef, i32 %v, i32 0
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%b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
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%i = add <2 x i32> %b2, <i32 2, i32 3>
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ret <2 x i32> %i
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; CHECK-LABEL: @test80
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; CHECK: addi
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; CHECK: addi
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; CHECK: lxvd2x
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; CHECK-NOT: stxvd2x
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; FIXME: We still make one vector for each vector element and this shuffle them
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; together instead of just composing one vector on the stack.
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; CHECK: blr
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}
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