From 663e484df9b12e2366ffb625dd3d594ca416e39f Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 16 Jul 2014 15:34:07 +0000 Subject: [PATCH] [mips][fp64a] Temporarily disable odd-numbered double-precision registers when using the FP64A ABI. Summary: A few instructions (mostly cvt.d.w and similar) are causing problems with -mfp64 and -mno-odd-spreg and it looks like fixing it properly may take several weeks. In the meantime, let's disable the odd-numbered double-precision registers so that the generated code is at least valid. The problem is that instructions like cvt.d.w read from the 32-bit low subregister of a double-precision FPU register. This often leads to the compiler to inserting moves to transfer a GPR32 to a FGR32 using mtc1. Such moves violate the rules against 32-bit writes to odd-numbered FPU registers imposed by -mno-odd-spreg. By disabling the odd-numbered double-precision registers, it becomes impossible for the 32-bit low subregister to be odd-numbered. This fixes numerous test-suite failures when compiling for the FP64A ABI ('-mfp64 -mno-odd-spreg'). There is no LLVM test case because it's difficult to test that odd-numbered FPU registers are not allocatable. Instead, we depend on the assembler (GAS and -fintegrated-as) raising errors when the rules are violated. Differential Revision: http://reviews.llvm.org/D4532 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213160 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsRegisterInfo.td | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 6323da37885..74dfa4fe7d9 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -341,9 +341,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; // Used to reserve odd registers when given -mattr=+nooddspreg +// FIXME: Remove double precision registers from this set. def OddSP : RegisterClass<"Mips", [f32], 32, (add (decimate (sequence "F%u", 1, 31), 2), - (decimate (sequence "F_HI%u", 1, 31), 2))>, + (decimate (sequence "F_HI%u", 1, 31), 2), + (decimate (sequence "D%u", 1, 15), 2), + (decimate (sequence "D%u_64", 1, 31), 2))>, Unallocatable; // FP control registers.