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Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -116,7 +116,7 @@ public:
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bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode);
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bool SelectAddrMode5(SDValue N, SDValue &Base,
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SDValue &Offset);
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bool SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align);
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bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
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bool SelectAddrModePC(SDValue N, SDValue &Offset,
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SDValue &Label);
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@ -222,6 +222,9 @@ private:
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SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
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SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
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SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
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// Get the alignment operand for a NEON VLD or VST instruction.
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SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
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};
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}
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@ -769,10 +772,26 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align){
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bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
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SDValue &Align) {
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Addr = N;
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// Default to no alignment.
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Align = CurDAG->getTargetConstant(0, MVT::i32);
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unsigned Alignment = 0;
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if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
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// This case occurs only for VLD1-lane/dup and VST1-lane instructions.
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// The maximum alignment is equal to the memory size being referenced.
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unsigned LSNAlign = LSN->getAlignment();
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unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
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if (LSNAlign > MemSize && MemSize > 1)
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Alignment = MemSize;
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} else {
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// All other uses of addrmode6 are for intrinsics. For now just record
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// the raw alignment value; it will be refined later based on the legal
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// alignment operands for the intrinsic.
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Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
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}
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Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
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return true;
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}
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@ -1261,19 +1280,23 @@ SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
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/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
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/// of a NEON VLD or VST instruction. The supported values depend on the
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/// number of registers being loaded.
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static unsigned GetVLDSTAlign(SDNode *N, unsigned NumVecs, bool is64BitVector) {
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SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
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bool is64BitVector) {
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unsigned NumRegs = NumVecs;
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if (!is64BitVector && NumVecs < 3)
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NumRegs *= 2;
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unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
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unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
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if (Alignment >= 32 && NumRegs == 4)
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return 32;
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if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
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return 16;
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if (Alignment >= 8)
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return 8;
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return 0;
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Alignment = 32;
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else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
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Alignment = 16;
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else if (Alignment >= 8)
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Alignment = 8;
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else
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Alignment = 0;
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return CurDAG->getTargetConstant(Alignment, MVT::i32);
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}
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SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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@ -1283,15 +1306,13 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, Align;
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if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
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if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
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return NULL;
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SDValue Chain = N->getOperand(0);
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EVT VT = N->getValueType(0);
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bool is64BitVector = VT.is64BitVector();
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unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
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Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
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Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
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unsigned OpcodeIndex;
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switch (VT.getSimpleVT().SimpleTy) {
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@ -1397,15 +1418,13 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, Align;
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if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
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if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
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return NULL;
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SDValue Chain = N->getOperand(0);
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EVT VT = N->getOperand(3).getValueType();
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bool is64BitVector = VT.is64BitVector();
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unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
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Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
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Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
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unsigned OpcodeIndex;
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switch (VT.getSimpleVT().SimpleTy) {
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@ -1520,7 +1539,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, Align;
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if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
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if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
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return NULL;
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SDValue Chain = N->getOperand(0);
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@ -1529,16 +1548,18 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
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EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
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bool is64BitVector = VT.is64BitVector();
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unsigned Alignment = 0;
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if (NumVecs != 3) {
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unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
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Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
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unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
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if (Alignment > NumBytes)
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Alignment = NumBytes;
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// Alignment must be a power of two; make sure of that.
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Alignment = (Alignment & -Alignment);
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if (Alignment > 1)
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Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
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if (Alignment == 1)
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Alignment = 0;
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}
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Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
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unsigned OpcodeIndex;
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switch (VT.getSimpleVT().SimpleTy) {
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@ -469,7 +469,7 @@ def addrmode5 : Operand<i32>,
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// addrmode6 := reg with optional writeback
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//
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def addrmode6 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode6", []> {
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ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
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let PrintMethod = "printAddrMode6Operand";
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let MIOperandInfo = (ops GPR:$addr, i32imm);
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}
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@ -2,27 +2,30 @@
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define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vld1lanei8:
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;Check the (default) alignment value.
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;CHECK: vld1.8 {d16[3]}, [r0]
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%tmp1 = load <8 x i8>* %B
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%tmp2 = load i8* %A, align 1
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%tmp2 = load i8* %A, align 8
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%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vld1lanei16:
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;CHECK: vld1.16 {d16[2]}, [r0]
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vld1.16 {d16[2]}, [r0, :16]
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%tmp1 = load <4 x i16>* %B
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%tmp2 = load i16* %A, align 2
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%tmp2 = load i16* %A, align 8
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%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vld1lanei32:
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;CHECK: vld1.32 {d16[1]}, [r0]
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vld1.32 {d16[1]}, [r0, :32]
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%tmp1 = load <2 x i32>* %B
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%tmp2 = load i32* %A, align 4
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%tmp2 = load i32* %A, align 8
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%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
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ret <2 x i32> %tmp3
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}
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@ -31,25 +34,25 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK: vld1laneQi8:
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;CHECK: vld1.8 {d17[1]}, [r0]
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%tmp1 = load <16 x i8>* %B
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%tmp2 = load i8* %A, align 1
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%tmp2 = load i8* %A, align 8
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%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vld1laneQi16:
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;CHECK: vld1.16 {d17[1]}, [r0]
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;CHECK: vld1.16 {d17[1]}, [r0, :16]
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%tmp1 = load <8 x i16>* %B
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%tmp2 = load i16* %A, align 2
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%tmp2 = load i16* %A, align 8
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%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vld1laneQi32:
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;CHECK: vld1.32 {d17[1]}, [r0]
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;CHECK: vld1.32 {d17[1]}, [r0, :32]
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%tmp1 = load <4 x i32>* %B
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%tmp2 = load i32* %A, align 4
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%tmp2 = load i32* %A, align 8
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%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
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ret <4 x i32> %tmp3
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}
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