mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
[X86] Remove some unused multiclasses from AVX512 instruction file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
49afc9109e
commit
6660dcedd3
@ -4551,107 +4551,6 @@ let Predicates = [HasAVX512] in {
|
||||
}
|
||||
|
||||
|
||||
multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
|
||||
X86MemOperand x86memop, RegisterClass RC,
|
||||
PatFrag mem_frag32, PatFrag mem_frag64,
|
||||
Intrinsic V4F32Int, Intrinsic V2F64Int,
|
||||
CD8VForm VForm> {
|
||||
let ExeDomain = SSEPackedSingle in {
|
||||
// Intrinsic operation, reg.
|
||||
// Vector intrinsic operation, reg
|
||||
def PSr : AVX512AIi8<opcps, MRMSrcReg,
|
||||
(outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
|
||||
|
||||
// Vector intrinsic operation, mem
|
||||
def PSm : AVX512AIi8<opcps, MRMSrcMem,
|
||||
(outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst,
|
||||
(V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
|
||||
EVEX_CD8<32, VForm>;
|
||||
} // ExeDomain = SSEPackedSingle
|
||||
|
||||
let ExeDomain = SSEPackedDouble in {
|
||||
// Vector intrinsic operation, reg
|
||||
def PDr : AVX512AIi8<opcpd, MRMSrcReg,
|
||||
(outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
|
||||
|
||||
// Vector intrinsic operation, mem
|
||||
def PDm : AVX512AIi8<opcpd, MRMSrcMem,
|
||||
(outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set RC:$dst,
|
||||
(V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
|
||||
EVEX_CD8<64, VForm>;
|
||||
} // ExeDomain = SSEPackedDouble
|
||||
}
|
||||
|
||||
multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
|
||||
string OpcodeStr,
|
||||
Intrinsic F32Int,
|
||||
Intrinsic F64Int> {
|
||||
let ExeDomain = GenericDomain in {
|
||||
// Operation, reg.
|
||||
let hasSideEffects = 0 in
|
||||
def SSr : AVX512AIi8<opcss, MRMSrcReg,
|
||||
(outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>;
|
||||
|
||||
// Intrinsic operation, reg.
|
||||
let isCodeGenOnly = 1 in
|
||||
def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
|
||||
(outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
|
||||
|
||||
// Intrinsic operation, mem.
|
||||
def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
|
||||
(ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[(set VR128X:$dst, (F32Int VR128X:$src1,
|
||||
sse_load_f32:$src2, imm:$src3))]>,
|
||||
EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
// Operation, reg.
|
||||
let hasSideEffects = 0 in
|
||||
def SDr : AVX512AIi8<opcsd, MRMSrcReg,
|
||||
(outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>, VEX_W;
|
||||
|
||||
// Intrinsic operation, reg.
|
||||
let isCodeGenOnly = 1 in
|
||||
def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
|
||||
(outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
|
||||
VEX_W;
|
||||
|
||||
// Intrinsic operation, mem.
|
||||
def SDm : AVX512AIi8<opcsd, MRMSrcMem,
|
||||
(outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[(set VR128X:$dst,
|
||||
(F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
|
||||
VEX_W, EVEX_CD8<64, CD8VT1>;
|
||||
} // ExeDomain = GenericDomain
|
||||
}
|
||||
|
||||
multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
|
||||
X86MemOperand x86memop, RegisterClass RC,
|
||||
PatFrag mem_frag, Domain d> {
|
||||
|
Loading…
Reference in New Issue
Block a user