6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-02 22:30:36 +00:00
Code Issues Projects Releases Wiki Activity

Hexagon: add support for predicate-GPR copies.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anshuman Dasgupta 2013-02-13 22:56:34 +00:00
parent ff91f2ef47
commit 666e0d3bc4
2 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -426,6 +426,18 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
return;
}
if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
Hexagon::IntRegsRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
addReg(SrcReg, getKillRegState(KillSrc));
return;
}
if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
Hexagon::PredRegsRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
addReg(SrcReg, getKillRegState(KillSrc));
return;
}
llvm_unreachable("Unimplemented");
}

8
test/CodeGen/Hexagon/predicate-copy.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
; CHECK: r{{[0-9]+}} = p{{[0-9]+}}
define i1 @foo() {
entry:
ret i1 false
}