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Fix unsupported addressing mode assertion for pld

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Summary:
This commit gives an address mode to the PLD instruction. We
were getting an assertion failure in the frame lowering code
because we had code that was doing a pld of a stack allocated
address. The frame lowering was checking the address mode and
then asserting because pld had none defined.

This commit fixes pld for arm mode. There was a previous fix for
thumb mode in a separate commit. The commit for thumb mode
added a test in a separate file because it would otherwise fail
for arm. This commit moves the thumb test back into the prefetch.ll
file and adds the corresponding arm test.

Differential Revision: http://llvm-reviews.chandlerc.com/D2622


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200248 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Peixotto
2014-01-27 21:39:04 +00:00
parent eea2f89d5d
commit 66742f023c
4 changed files with 24 additions and 24 deletions
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18
test/CodeGen/ARM/prefetch.ll
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@ -75,3 +75,21 @@ entry:
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
ret void
}
define void @t6() {
entry:
;ARM-LABEL: t6:
;ARM: pld [sp]
;ARM: pld [sp, #50]
;THUMB2-LABEL: t6:
;THUMB2: pld [sp]
;THUMB2: pld [sp, #50]
%red = alloca [100 x i8], align 1
%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50
call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
ret void
}