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Add initial support for fast isel of instructions that have inputs pinned to physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,6 +18,7 @@
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#include "X86ISelLowering.h"
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#include "X86ISelLowering.h"
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#include "X86FastISel.h"
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#include "X86FastISel.h"
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#include "X86TargetMachine.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "X86GenFastISel.inc"
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#include "X86GenFastISel.inc"
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namespace llvm {
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namespace llvm {
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@ -44,6 +44,16 @@ using namespace llvm;
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namespace {
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namespace {
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/// InstructionMemo - This class holds additional information about an
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/// instruction needed to emit code for it.
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///
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struct InstructionMemo {
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std::string Name;
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const CodeGenRegisterClass *RC;
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unsigned char SubRegNo;
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std::vector<std::string>* PhysRegs;
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};
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/// OperandsSignature - This class holds a description of a list of operand
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/// OperandsSignature - This class holds a description of a list of operand
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/// types. It has utility methods for emitting text based on the operands.
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/// types. It has utility methods for emitting text based on the operands.
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///
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///
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@ -103,15 +113,17 @@ struct OperandsSignature {
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if (!OpDI)
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if (!OpDI)
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return false;
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return false;
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Record *OpLeafRec = OpDI->getDef();
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Record *OpLeafRec = OpDI->getDef();
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// TODO: handle instructions which have physreg operands.
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if (OpLeafRec->isSubClassOf("Register"))
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return false;
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// For now, the only other thing we accept is register operands.
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// For now, the only other thing we accept is register operands.
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if (!OpLeafRec->isSubClassOf("RegisterClass"))
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const CodeGenRegisterClass *RC = 0;
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if (OpLeafRec->isSubClassOf("RegisterClass"))
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RC = &Target.getRegisterClass(OpLeafRec);
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else if (OpLeafRec->isSubClassOf("Register"))
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RC = Target.getRegisterClassForRegister(OpLeafRec);
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else
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return false;
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return false;
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// For now, require the register operands' register classes to all
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// For now, require the register operands' register classes to all
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// be the same.
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// be the same.
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const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
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if (!RC)
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if (!RC)
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return false;
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return false;
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// For now, all the operands must have the same register class.
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// For now, all the operands must have the same register class.
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@ -142,6 +154,27 @@ struct OperandsSignature {
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}
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}
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}
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}
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void PrintArguments(std::ostream &OS,
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const std::vector<std::string>& PR) const {
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assert(PR.size() == Operands.size());
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (PR[i] != "") {
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OS << PR[i];
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} else if (Operands[i] == "r") {
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OS << "Op" << i;
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} else if (Operands[i] == "i") {
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OS << "imm" << i;
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} else if (Operands[i] == "f") {
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OS << "f" << i;
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} else {
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assert("Unknown operand kind!");
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abort();
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintArguments(std::ostream &OS) const {
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void PrintArguments(std::ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] == "r") {
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if (Operands[i] == "r") {
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@ -159,6 +192,7 @@ struct OperandsSignature {
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}
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}
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}
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}
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void PrintManglingSuffix(std::ostream &OS) const {
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void PrintManglingSuffix(std::ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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OS << Operands[i];
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OS << Operands[i];
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@ -166,15 +200,6 @@ struct OperandsSignature {
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}
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}
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};
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};
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/// InstructionMemo - This class holds additional information about an
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/// instruction needed to emit code for it.
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///
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struct InstructionMemo {
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std::string Name;
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const CodeGenRegisterClass *RC;
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unsigned char SubRegNo;
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};
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class FastISelMap {
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class FastISelMap {
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typedef std::map<std::string, InstructionMemo> PredMap;
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typedef std::map<std::string, InstructionMemo> PredMap;
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typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
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typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
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@ -276,6 +301,41 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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if (!Operands.initialize(InstPatNode, Target, VT))
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if (!Operands.initialize(InstPatNode, Target, VT))
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continue;
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continue;
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std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
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if (!InstPatNode->isLeaf() &&
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(InstPatNode->getOperator()->getName() == "imm" ||
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InstPatNode->getOperator()->getName() == "fpimmm"))
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PhysRegInputs->push_back("");
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else if (!InstPatNode->isLeaf()) {
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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if (!Op->isLeaf()) {
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PhysRegInputs->push_back("");
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continue;
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}
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DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
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Record *OpLeafRec = OpDI->getDef();
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std::string PhysReg;
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if (OpLeafRec->isSubClassOf("Register")) {
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PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
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"Namespace")->getValue())->getValue();
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PhysReg += "::";
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std::vector<CodeGenRegister> Regs = Target.getRegisters();
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for (unsigned i = 0; i < Regs.size(); ++i) {
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if (Regs[i].TheDef == OpLeafRec) {
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PhysReg += Regs[i].getName();
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break;
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}
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}
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}
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PhysRegInputs->push_back(PhysReg);
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}
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} else
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PhysRegInputs->push_back("");
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// Get the predicate that guards this pattern.
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// Get the predicate that guards this pattern.
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std::string PredicateCheck = Pattern.getPredicateCheck();
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std::string PredicateCheck = Pattern.getPredicateCheck();
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@ -283,7 +343,8 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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InstructionMemo Memo = {
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InstructionMemo Memo = {
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Pattern.getDstPattern()->getOperator()->getName(),
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Pattern.getDstPattern()->getOperator()->getName(),
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DstRC,
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DstRC,
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SubRegNo
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SubRegNo,
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PhysRegInputs
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};
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};
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assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
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assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
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"Duplicate pattern!");
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"Duplicate pattern!");
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@ -422,10 +483,20 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
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"Multiple instructions match, at least one has "
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"Multiple instructions match, at least one has "
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"a predicate and at least one doesn't!");
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"a predicate and at least one doesn't!");
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} else {
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} else {
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OS << " if (" + PredicateCheck + ")\n";
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OS << " if (" + PredicateCheck + ") {\n";
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OS << " ";
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OS << " ";
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HasPred = true;
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HasPred = true;
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}
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}
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for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
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if ((*Memo.PhysRegs)[i] != "")
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OS << " TII.copyRegToReg(*MBB, MBB->end(), "
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<< (*Memo.PhysRegs)[i] << ", Op" << i << ", "
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<< "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
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<< (*Memo.PhysRegs)[i] << "), "
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<< "MRI.getRegClass(Op" << i << "));\n";
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}
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OS << " return FastEmitInst_";
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OS << " return FastEmitInst_";
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if (Memo.SubRegNo == (unsigned char)~0) {
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if (Memo.SubRegNo == (unsigned char)~0) {
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Operands.PrintManglingSuffix(OS);
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Operands.PrintManglingSuffix(OS);
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OS << InstNS << Memo.RC->getName() << "RegisterClass";
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OS << InstNS << Memo.RC->getName() << "RegisterClass";
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if (!Operands.empty())
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if (!Operands.empty())
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OS << ", ";
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OS << ", ";
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Operands.PrintArguments(OS);
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Operands.PrintArguments(OS, *Memo.PhysRegs);
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OS << ");\n";
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OS << ");\n";
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} else {
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} else {
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OS << "extractsubreg(Op0, ";
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OS << "extractsubreg(Op0, ";
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OS << (unsigned)Memo.SubRegNo;
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OS << (unsigned)Memo.SubRegNo;
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OS << ");\n";
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OS << ");\n";
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}
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}
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if (HasPred)
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OS << "}\n";
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}
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}
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// Return 0 if none of the predicates were satisfied.
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// Return 0 if none of the predicates were satisfied.
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if (HasPred)
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if (HasPred)
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@ -500,10 +575,20 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
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"Multiple instructions match, at least one has "
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"Multiple instructions match, at least one has "
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"a predicate and at least one doesn't!");
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"a predicate and at least one doesn't!");
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} else {
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} else {
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OS << " if (" + PredicateCheck + ")\n";
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OS << " if (" + PredicateCheck + ") {\n";
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OS << " ";
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OS << " ";
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HasPred = true;
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HasPred = true;
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}
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}
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for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
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if ((*Memo.PhysRegs)[i] != "")
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OS << " TII.copyRegToReg(*MBB, MBB->end(), "
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<< (*Memo.PhysRegs)[i] << ", Op" << i << ", "
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<< "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
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<< (*Memo.PhysRegs)[i] << "), "
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<< "MRI.getRegClass(Op" << i << "));\n";
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}
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OS << " return FastEmitInst_";
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OS << " return FastEmitInst_";
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if (Memo.SubRegNo == (unsigned char)~0) {
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if (Memo.SubRegNo == (unsigned char)~0) {
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@ -512,13 +597,16 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
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OS << InstNS << Memo.RC->getName() << "RegisterClass";
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OS << InstNS << Memo.RC->getName() << "RegisterClass";
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if (!Operands.empty())
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if (!Operands.empty())
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OS << ", ";
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OS << ", ";
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Operands.PrintArguments(OS);
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Operands.PrintArguments(OS, *Memo.PhysRegs);
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OS << ");\n";
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OS << ");\n";
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} else {
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} else {
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OS << "extractsubreg(Op0, ";
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OS << "extractsubreg(Op0, ";
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OS << (unsigned)Memo.SubRegNo;
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OS << (unsigned)Memo.SubRegNo;
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OS << ");\n";
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OS << ");\n";
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}
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}
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if (HasPred)
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OS << " }\n";
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}
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}
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// Return 0 if none of the predicates were satisfied.
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// Return 0 if none of the predicates were satisfied.
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