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Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1604,7 +1604,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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VT = N->getOperand(3).getValueType();
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst3 type");
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case MVT::v8i8: Opc = ARM::VST3d8; break;
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case MVT::v4i16: Opc = ARM::VST3d16; break;
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@ -1617,6 +1619,50 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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N->getOperand(5), Chain };
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
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}
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// Quad registers are stored with two separate instructions, where one
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// stores the even registers and the other stores the odd registers.
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EVT RegVT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst3 type");
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case MVT::v16i8:
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Opc = ARM::VST3q8a; Opc2 = ARM::VST3q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VST3q16a; Opc2 = ARM::VST3q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2i32; break;
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}
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SDValue Chain = N->getOperand(0);
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(3));
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SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(4));
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SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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N->getOperand(5));
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, D0, D2, D4, Chain };
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, OpsA, 7);
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Chain = SDValue(VStA, 1);
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SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(3));
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SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(4));
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SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
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N->getOperand(5));
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MemAddr = SDValue(VStA, 0);
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const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc, D1, D3, D5, Chain };
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SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
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MVT::Other, OpsB, 7);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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}
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case Intrinsic::arm_neon_vst4: {
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SDValue MemAddr, MemUpdate, MemOpc;
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@ -335,11 +335,26 @@ class VST3D<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
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IIC_VST,
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!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
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class VST3WB<string OpcodeStr>
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: NLdSt<(outs GPR:$wb), (ins addrmode6:$addr, DPR:$src1, DPR:$src2,
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DPR:$src3), IIC_VST,
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!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"),
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"$addr.addr = $wb", []>;
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def VST3d8 : VST3D<"vst3.8">;
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def VST3d16 : VST3D<"vst3.16">;
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def VST3d32 : VST3D<"vst3.32">;
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// vst3 to double-spaced even registers.
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def VST3q8a : VST3WB<"vst3.8">;
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def VST3q16a : VST3WB<"vst3.16">;
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def VST3q32a : VST3WB<"vst3.32">;
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// vst3 to double-spaced odd registers.
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def VST3q8b : VST3WB<"vst3.8">;
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def VST3q16b : VST3WB<"vst3.16">;
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def VST3q32b : VST3WB<"vst3.32">;
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// VST4 : Vector Store (multiple 4-element structures)
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class VST4D<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr,
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@ -146,6 +146,24 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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NumRegs = 3;
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return true;
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case ARM::VST3q8a:
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case ARM::VST3q16a:
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case ARM::VST3q32a:
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FirstOpnd = 4;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST3q8b:
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case ARM::VST3q16b:
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case ARM::VST3q32b:
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FirstOpnd = 4;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST4d8:
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case ARM::VST4d16:
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case ARM::VST4d32:
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@ -32,7 +32,48 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind {
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ret void
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}
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define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK: vst3Qi8:
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;CHECK: vst3.8
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;CHECK: vst3.8
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%tmp1 = load <16 x i8>* %B
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call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1)
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ret void
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}
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define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vst3Qi16:
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;CHECK: vst3.16
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;CHECK: vst3.16
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst3.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1)
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ret void
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}
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define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vst3Qi32:
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;CHECK: vst3.32
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;CHECK: vst3.32
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst3.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1)
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ret void
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}
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define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vst3Qf:
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;CHECK: vst3.32
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;CHECK: vst3.32
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%tmp1 = load <4 x float>* %B
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call void @llvm.arm.neon.vst3.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1)
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ret void
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}
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declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind
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declare void @llvm.arm.neon.vst3.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>) nounwind
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declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>) nounwind
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declare void @llvm.arm.neon.vst3.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>) nounwind
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declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>) nounwind
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declare void @llvm.arm.neon.vst3.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>) nounwind
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declare void @llvm.arm.neon.vst3.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>) nounwind
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declare void @llvm.arm.neon.vst3.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>) nounwind
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