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Fixes an issue reported by -verify-machineinstrs.
Patch by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143064 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11784,6 +11784,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
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bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
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tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
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SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
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sizeVReg = MI->getOperand(1).getReg(),
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physSPReg = Is64Bit ? X86::RSP : X86::ESP;
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@ -11801,19 +11802,19 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
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// Add code to the main basic block to check if the stack limit has been hit,
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// and if so, jump to mallocMBB otherwise to bumpMBB.
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BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
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BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
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BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
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.addReg(tmpSPVReg).addReg(sizeVReg);
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BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
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.addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
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.addReg(tmpSPVReg);
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.addReg(SPLimitVReg);
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BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
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// bumpMBB simply decreases the stack pointer, since we know the current
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// stacklet has enough space.
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BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
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.addReg(tmpSPVReg);
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.addReg(SPLimitVReg);
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BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
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.addReg(tmpSPVReg);
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.addReg(SPLimitVReg);
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BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
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// Calls into a routine in libgcc to allocate more space from the heap.
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@ -112,14 +112,14 @@ let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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// allocated by bumping the stack pointer. Otherwise memory is allocated from
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// the heap.
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let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in
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let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
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"# variable sized alloca for segmented stacks",
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[(set GR32:$dst,
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(X86SegAlloca GR32:$size))]>,
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Requires<[In32BitMode]>;
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let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in
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let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
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def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
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"# variable sized alloca for segmented stacks",
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[(set GR64:$dst,
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@ -30,6 +30,10 @@ false:
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; X32-NEXT: addl $8, %esp
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; X32-NEXT: ret
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; X32: movl %esp, %eax
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; X32-NEXT: subl %ecx, %eax
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; X32-NEXT: cmpl %eax, %gs:48
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; X32: movl %eax, %esp
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; X32: subl $12, %esp
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@ -47,14 +51,15 @@ false:
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; X64-NEXT: callq __morestack
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; X64-NEXT: ret
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; X64: movq %rsp, %rax
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; X64-NEXT: subq %rcx, %rax
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; X64-NEXT: cmpq %rax, %fs:112
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; X64: movq %rsp, %rdi
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; X64-NEXT: subq %rax, %rdi
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; X64-NEXT: cmpq %rdi, %fs:112
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; X64: movq %rax, %rsp
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; X64: movq %rdi, %rsp
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; X64: movq %rcx, %rdi
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; X64: movq %rax, %rdi
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; X64-NEXT: callq __morestack_allocate_stack_space
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; X64-NEXT: movq %rax, %rdi
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}
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