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PPC: Implement efficient lowering of sign_extend_inreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172269 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -61,6 +61,8 @@ class VectorLegalizer {
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// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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// SINT_TO_FLOAT and SHR on vectors isn't legal.
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// SINT_TO_FLOAT and SHR on vectors isn't legal.
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
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SDValue ExpandSEXTINREG(SDValue Op);
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// Implement vselect in terms of XOR, AND, OR when blend is not supported
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// Implement vselect in terms of XOR, AND, OR when blend is not supported
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// by the target.
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// by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandVSELECT(SDValue Op);
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@ -262,7 +264,9 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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// FALL THROUGH
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// FALL THROUGH
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}
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}
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case TargetLowering::Expand:
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case TargetLowering::Expand:
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if (Node->getOpcode() == ISD::VSELECT)
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if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
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Result = ExpandSEXTINREG(Op);
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else if (Node->getOpcode() == ISD::VSELECT)
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Result = ExpandVSELECT(Op);
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Result = ExpandVSELECT(Op);
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else if (Node->getOpcode() == ISD::SELECT)
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else if (Node->getOpcode() == ISD::SELECT)
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Result = ExpandSELECT(Op);
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Result = ExpandSELECT(Op);
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@ -501,6 +505,26 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
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return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
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return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
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}
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}
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SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
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EVT VT = Op.getValueType();
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// Make sure that the SRA and SRL instructions are available.
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if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
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TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
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return DAG.UnrollVectorOp(Op.getNode());
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DebugLoc DL = Op.getDebugLoc();
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EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
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unsigned BW = VT.getScalarType().getSizeInBits();
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unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
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SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
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Op = Op.getOperand(0);
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Op = DAG.getNode(ISD::SRL, DL, VT, Op, ShiftSz);
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return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
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}
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SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
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SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
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// Implement VSELECT in terms of XOR, AND, OR
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// Implement VSELECT in terms of XOR, AND, OR
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// on platforms which do not support blend natively.
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// on platforms which do not support blend natively.
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@ -15,55 +15,9 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
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ret <16 x i8> %c
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ret <16 x i8> %c
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}
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}
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; CHECK: v16si8_sext_in_reg:
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; CHECK: v16si8_sext_in_reg:
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vsrb
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; CHECK: lbz
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; CHECK: vsrab
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; CHECK: stb
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; CHECK: blr
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; The zero extend uses a more clever logic: a vector splat
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; The zero extend uses a more clever logic: a vector splat
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; and a logic and to set higher bits to 0.
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; and a logic and to set higher bits to 0.
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@ -83,31 +37,9 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
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ret <8 x i16> %c
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ret <8 x i16> %c
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}
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}
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; CHECK: v8si16_sext_in_reg:
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; CHECK: v8si16_sext_in_reg:
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vsrh
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; CHECK: lhz
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; CHECK: vsrah
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; CHECK: sth
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; CHECK: blr
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; Same as v8si16_sext_in_reg, but instead of creating the mask
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; Same as v8si16_sext_in_reg, but instead of creating the mask
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; with a splat, loads it from memory.
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; with a splat, loads it from memory.
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@ -129,19 +61,9 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
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ret <4 x i32> %c
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ret <4 x i32> %c
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}
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}
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; CHECK: v4si32_sext_in_reg:
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; CHECK: v4si32_sext_in_reg:
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vsrw
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; CHECK: lha
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; CHECK: vsraw
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; CHECK: stw
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; CHECK: blr
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; Same as v8si16_sext_in_reg.
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; Same as v8si16_sext_in_reg.
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define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
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define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
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