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- Added a few target hooks to generate load / store instructions from / to any

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address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-10-05 01:32:41 +00:00
parent 39305cf553
commit 66f0f64082
11 changed files with 505 additions and 85 deletions
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55
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -48,6 +48,34 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
assert(0 && "Can't store this register to stack slot");
}
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const {
unsigned Opc = 0;
if (RC == SP::IntRegsRegisterClass)
Opc = SP::STri;
else if (RC == SP::FPRegsRegisterClass)
Opc = SP::STFri;
else if (RC == SP::DFPRegsRegisterClass)
Opc = SP::STDFri;
else
assert(0 && "Can't load this register");
MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
MIB.addReg(SrcReg, false, false, true);
NewMIs.push_back(MIB);
return;
}
void SparcRegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
@ -62,6 +90,33 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
assert(0 && "Can't load this register from stack slot");
}
void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const {
unsigned Opc = 0;
if (RC == SP::IntRegsRegisterClass)
Opc = SP::LDri;
else if (RC == SP::FPRegsRegisterClass)
Opc = SP::LDFri;
else if (RC == SP::DFPRegsRegisterClass)
Opc = SP::LDDFri;
else
assert(0 && "Can't load this register");
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
return;
}
void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,

10
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -35,11 +35,21 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,