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Convert asmprinter to new style of instruction printer

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Start asmprintergen'ifying machine instrs with memory operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15646 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-11 02:25:00 +00:00
parent 1caef2c0a9
commit 66fa1dcf90
2 changed files with 49 additions and 8 deletions
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18
lib/Target/X86/X86AsmPrinter.cpp
View File

@ -105,7 +105,8 @@ namespace {
bool printInstruction(const MachineInstr *MI);
// This method is used by the tablegen'erated instruction printer.
void printOperand(const MachineOperand &MO, MVT::ValueType VT) {
void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_MachineRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
// Bug Workaround: See note in Printer::doInitialization about %.
@ -115,6 +116,21 @@ namespace {
}
}
void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) {
switch (VT) {
default: assert(0 && "Unknown arg size!");
case MVT::i8: O << "BYTE PTR "; break;
case MVT::i16: O << "WORD PTR "; break;
case MVT::i32:
case MVT::f32: O << "DWORD PTR "; break;
case MVT::i64:
case MVT::f64: O << "QWORD PTR "; break;
case MVT::f80: O << "XWORD PTR "; break;
}
printMemReference(MI, OpNo);
}
bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC);
void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);

39
lib/Target/X86/X86InstrInfo.td
View File

@ -13,6 +13,24 @@
//
//===----------------------------------------------------------------------===//
// *mem - Operand definitions for the funky X86 addressing mode operands.
//
def i8mem : Operand<i8> {
let NumMIOperands = 4;
let PrintMethod = "printMemoryOperand";
}
def i16mem : Operand<i16> {
let NumMIOperands = 4;
let PrintMethod = "printMemoryOperand";
}
def i32mem : Operand<i32> {
let NumMIOperands = 4;
let PrintMethod = "printMemoryOperand";
}
// Format specifies the encoding used by the instruction. This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
@ -219,7 +237,8 @@ def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
(ops R32:$src1, R32:$src2), "xchg $src1, $src2">;
def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
def XCHG8mr : Im8 <"", 0x86, MRMDestMem>, // xchg [mem8], R8
II<(ops i8mem:$src1, R8:$src2), "xchg $src1, $src2">;
def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
@ -289,13 +308,19 @@ def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8]
def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize; // R16 = [mem16]
def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>; // R32 = [mem32]
def MOV8rm : Im8 <"", 0x8A, MRMSrcMem>, // R8 = [mem8]
II<(ops R8 :$dst, i8mem :$src), "mov $dst, $src">;
def MOV16rm : Im16<"", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16]
II<(ops R16:$dst, i16mem:$src), "mov $dst, $src">;
def MOV32rm : Im32<"", 0x8B, MRMSrcMem>, // R32 = [mem32]
II<(ops R32:$dst, i32mem:$src), "mov $dst, $src">;
def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8
def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16
def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
def MOV8mr : Im8 <"", 0x88, MRMDestMem>, // [mem8] = R8
II<(ops i8mem :$dst, R8 :$src), "mov $dst, $src">;
def MOV16mr : Im16<"", 0x89, MRMDestMem>, OpSize, // [mem16] = R16
II<(ops i16mem:$dst, R16:$src), "mov $dst, $src">;
def MOV32mr : Im32<"", 0x89, MRMDestMem>, // [mem32] = R32
II<(ops i32mem:$dst, R32:$src), "mov $dst, $src">;
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...