From 67032b27cddbb07134e128074bd23ae95384367c Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Sat, 22 Sep 2012 00:06:06 +0000
Subject: [PATCH] MIPS DSP: Add predicates and instruction template.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164434 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/MipsDSPInstrFormats.td | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 lib/Target/Mips/MipsDSPInstrFormats.td

diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td
new file mode 100644
index 00000000000..d9bcccc6176
--- /dev/null
+++ b/lib/Target/Mips/MipsDSPInstrFormats.td
@@ -0,0 +1,25 @@
+//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+def HasDSP : Predicate<"Subtarget.hasDSP()">,
+             AssemblerPredicate<"FeatureDSP">;
+def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
+               AssemblerPredicate<"FeatureDSPR2">;
+
+// Fields.
+class Field6<bits<6> val> {
+  bits<6> V = val;
+}
+
+def SPECIAL3_OPCODE : Field6<0b011111>;
+def REGIMM_OPCODE : Field6<0b000001>;
+
+class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+  let Predicates = [HasDSP];
+}