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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159035 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-06-22 22:07:19 +00:00
parent bfd752f310
commit 670712ca3f
1 changed files with 8 additions and 8 deletions
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16
lib/Target/X86/X86InstrBuilder.h
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@ -55,11 +55,11 @@ struct X86AddressMode {
: BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) { : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
Base.Reg = 0; Base.Reg = 0;
} }
void getFullAddress(SmallVectorImpl<MachineOperand> &MO) { void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8); assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
if (BaseType == X86AddressMode::RegBase) if (BaseType == X86AddressMode::RegBase)
MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
false, false, false, 0, false)); false, false, false, 0, false));
@ -67,16 +67,16 @@ struct X86AddressMode {
assert(BaseType == X86AddressMode::FrameIndexBase); assert(BaseType == X86AddressMode::FrameIndexBase);
MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
} }
MO.push_back(MachineOperand::CreateImm(Scale)); MO.push_back(MachineOperand::CreateImm(Scale));
MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
false, false, false, 0, false)); false, false, false, 0, false));
if (GV) if (GV)
MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
else else
MO.push_back(MachineOperand::CreateImm(Disp)); MO.push_back(MachineOperand::CreateImm(Disp));
MO.push_back(MachineOperand::CreateReg(0, false, false, MO.push_back(MachineOperand::CreateReg(0, false, false,
false, false, false, 0, false)); false, false, false, 0, false));
} }
@ -122,7 +122,7 @@ static inline const MachineInstrBuilder &
addFullAddress(const MachineInstrBuilder &MIB, addFullAddress(const MachineInstrBuilder &MIB,
const X86AddressMode &AM) { const X86AddressMode &AM) {
assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8); assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
if (AM.BaseType == X86AddressMode::RegBase) if (AM.BaseType == X86AddressMode::RegBase)
MIB.addReg(AM.Base.Reg); MIB.addReg(AM.Base.Reg);
else { else {
@ -135,7 +135,7 @@ addFullAddress(const MachineInstrBuilder &MIB,
MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
else else
MIB.addImm(AM.Disp); MIB.addImm(AM.Disp);
return MIB.addReg(0); return MIB.addReg(0);
} }