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RFE encoding should also specify the "should be" encoding bits.

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rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-04 23:39:08 +00:00
parent b572830a52
commit 670a456c83
3 changed files with 49 additions and 28 deletions
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6
lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
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@ -141,6 +141,12 @@ static inline bool isUnaryDP(uint64_t TSFlags) {
return (TSFlags & ARMII::UnaryDP);
}
/// A NEON Domain instruction has cond field (Inst{31-28}) as 0b1111.
static inline bool isNEONDomain(uint64_t TSFlags) {
return (TSFlags & ARMII::DomainNEON) ||
(TSFlags & ARMII::DomainNEONA8);
}
/// This four-bit field describes the addressing mode used.
/// See also ARMBaseInstrInfo.h.
static inline unsigned getAddrMode(uint64_t TSFlags) {