diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index bee22816ce9..67633811361 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8419,38 +8419,30 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { // We are handling one of the integer comparisons here. Since SSE only has // GT and EQ comparisons for integer, swapping operands and multiple // operations may be required for some comparisons. - unsigned Opc = 0, EQOpc = 0, GTOpc = 0; + unsigned Opc = 0; bool Swap = false, Invert = false, FlipSigns = false; - switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { - default: break; - case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; - case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; - case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; - case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; - } - switch (SetCCOpcode) { default: break; case ISD::SETNE: Invert = true; - case ISD::SETEQ: Opc = EQOpc; break; + case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; case ISD::SETLT: Swap = true; - case ISD::SETGT: Opc = GTOpc; break; + case ISD::SETGT: Opc = X86ISD::PCMPGT; break; case ISD::SETGE: Swap = true; - case ISD::SETLE: Opc = GTOpc; Invert = true; break; + case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; case ISD::SETULT: Swap = true; - case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; + case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; case ISD::SETUGE: Swap = true; - case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; + case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; } if (Swap) std::swap(Op0, Op1); // Check that the operation in question is available (most are plain SSE2, // but PCMPGTQ and PCMPEQQ have different requirements). - if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42()) + if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) return SDValue(); - if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41()) + if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) return SDValue(); // Since SSE has no unsigned integer comparisons, we need to flip the sign @@ -10108,7 +10100,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { // R s>> 7 === R s< 0 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true, /* HasAVX2 */false, DAG, dl); - return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); + return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); } // R s>> a === ((R u>> a) ^ m) - m @@ -10152,7 +10144,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { // R s>> 7 === R s< 0 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, true /* HasAVX2 */, DAG, dl); - return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); + return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); } // R s>> a === ((R u>> a) ^ m) - m @@ -10198,7 +10190,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { // Turn 'a' into a mask suitable for VSELECT SDValue VSelM = DAG.getConstant(0x80, VT); SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); - OpVSel = DAG.getNode(X86ISD::PCMPEQB, dl, VT, OpVSel, VSelM); + OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); SDValue CM1 = DAG.getConstant(0x0f, VT); SDValue CM2 = DAG.getConstant(0x3f, VT); @@ -10213,7 +10205,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { // a += a Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); - OpVSel = DAG.getNode(X86ISD::PCMPEQB, dl, VT, OpVSel, VSelM); + OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); // r = VSELECT(r, psllw(r & (char16)63, 2), a); M = DAG.getNode(ISD::AND, dl, VT, R, CM2); @@ -10225,7 +10217,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { // a += a Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); - OpVSel = DAG.getNode(X86ISD::PCMPEQB, dl, VT, OpVSel, VSelM); + OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); // return VSELECT(r, r+r, a); R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, @@ -10945,14 +10937,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::VSRAI: return "X86ISD::VSRAI"; case X86ISD::CMPPD: return "X86ISD::CMPPD"; case X86ISD::CMPPS: return "X86ISD::CMPPS"; - case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; - case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; - case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; - case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; - case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; - case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; - case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; - case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; + case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; + case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; case X86ISD::ADD: return "X86ISD::ADD"; case X86ISD::SUB: return "X86ISD::SUB"; case X86ISD::ADC: return "X86ISD::ADC"; diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 6f84d8d0741..07efddccb82 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -233,8 +233,7 @@ namespace llvm { CMPPD, CMPPS, // PCMP* - Vector integer comparisons. - PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, - PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, + PCMPEQ, PCMPGT, // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. ADD, SUB, ADC, SBB, SMUL, diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index 369a5010640..5c39510e3f3 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -77,14 +77,8 @@ def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>; def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>; def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>; def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>; -def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>; -def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>; -def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>; -def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>; +def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; def X86vshl : SDNode<"X86ISD::VSHL", SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 412b7ac9d38..43ec63dc4aa 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -4092,35 +4092,35 @@ let Predicates = [HasAVX] in { defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, VR128, memopv2i64, i128mem, 0, 0>, VEX_4V; - def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)), + def : Pat<(v16i8 (X86pcmpeq VR128:$src1, VR128:$src2)), (VPCMPEQBrr VR128:$src1, VR128:$src2)>; - def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, + def : Pat<(v16i8 (X86pcmpeq VR128:$src1, (bc_v16i8 (memopv2i64 addr:$src2)))), (VPCMPEQBrm VR128:$src1, addr:$src2)>; - def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)), + def : Pat<(v8i16 (X86pcmpeq VR128:$src1, VR128:$src2)), (VPCMPEQWrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, + def : Pat<(v8i16 (X86pcmpeq VR128:$src1, (bc_v8i16 (memopv2i64 addr:$src2)))), (VPCMPEQWrm VR128:$src1, addr:$src2)>; - def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)), + def : Pat<(v4i32 (X86pcmpeq VR128:$src1, VR128:$src2)), (VPCMPEQDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, + def : Pat<(v4i32 (X86pcmpeq VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))), (VPCMPEQDrm VR128:$src1, addr:$src2)>; - def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)), + def : Pat<(v16i8 (X86pcmpgt VR128:$src1, VR128:$src2)), (VPCMPGTBrr VR128:$src1, VR128:$src2)>; - def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, + def : Pat<(v16i8 (X86pcmpgt VR128:$src1, (bc_v16i8 (memopv2i64 addr:$src2)))), (VPCMPGTBrm VR128:$src1, addr:$src2)>; - def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)), + def : Pat<(v8i16 (X86pcmpgt VR128:$src1, VR128:$src2)), (VPCMPGTWrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, + def : Pat<(v8i16 (X86pcmpgt VR128:$src1, (bc_v8i16 (memopv2i64 addr:$src2)))), (VPCMPGTWrm VR128:$src1, addr:$src2)>; - def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)), + def : Pat<(v4i32 (X86pcmpgt VR128:$src1, VR128:$src2)), (VPCMPGTDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, + def : Pat<(v4i32 (X86pcmpgt VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))), (VPCMPGTDrm VR128:$src1, addr:$src2)>; } @@ -4139,35 +4139,35 @@ let Predicates = [HasAVX2] in { defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d, VR256, memopv4i64, i256mem, 0, 0>, VEX_4V; - def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)), + def : Pat<(v32i8 (X86pcmpeq VR256:$src1, VR256:$src2)), (VPCMPEQBYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, + def : Pat<(v32i8 (X86pcmpeq VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)))), (VPCMPEQBYrm VR256:$src1, addr:$src2)>; - def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)), + def : Pat<(v16i16 (X86pcmpeq VR256:$src1, VR256:$src2)), (VPCMPEQWYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, + def : Pat<(v16i16 (X86pcmpeq VR256:$src1, (bc_v16i16 (memopv4i64 addr:$src2)))), (VPCMPEQWYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)), + def : Pat<(v8i32 (X86pcmpeq VR256:$src1, VR256:$src2)), (VPCMPEQDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, + def : Pat<(v8i32 (X86pcmpeq VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))), (VPCMPEQDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)), + def : Pat<(v32i8 (X86pcmpgt VR256:$src1, VR256:$src2)), (VPCMPGTBYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, + def : Pat<(v32i8 (X86pcmpgt VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)))), (VPCMPGTBYrm VR256:$src1, addr:$src2)>; - def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)), + def : Pat<(v16i16 (X86pcmpgt VR256:$src1, VR256:$src2)), (VPCMPGTWYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, + def : Pat<(v16i16 (X86pcmpgt VR256:$src1, (bc_v16i16 (memopv4i64 addr:$src2)))), (VPCMPGTWYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)), + def : Pat<(v8i32 (X86pcmpgt VR256:$src1, VR256:$src2)), (VPCMPGTDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, + def : Pat<(v8i32 (X86pcmpgt VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))), (VPCMPGTDYrm VR256:$src1, addr:$src2)>; } @@ -4188,35 +4188,35 @@ let Constraints = "$src1 = $dst" in { } // Constraints = "$src1 = $dst" let Predicates = [HasSSE2] in { - def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)), + def : Pat<(v16i8 (X86pcmpeq VR128:$src1, VR128:$src2)), (PCMPEQBrr VR128:$src1, VR128:$src2)>; - def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, + def : Pat<(v16i8 (X86pcmpeq VR128:$src1, (bc_v16i8 (memopv2i64 addr:$src2)))), (PCMPEQBrm VR128:$src1, addr:$src2)>; - def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)), + def : Pat<(v8i16 (X86pcmpeq VR128:$src1, VR128:$src2)), (PCMPEQWrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, + def : Pat<(v8i16 (X86pcmpeq VR128:$src1, (bc_v8i16 (memopv2i64 addr:$src2)))), (PCMPEQWrm VR128:$src1, addr:$src2)>; - def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)), + def : Pat<(v4i32 (X86pcmpeq VR128:$src1, VR128:$src2)), (PCMPEQDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, + def : Pat<(v4i32 (X86pcmpeq VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))), (PCMPEQDrm VR128:$src1, addr:$src2)>; - def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)), + def : Pat<(v16i8 (X86pcmpgt VR128:$src1, VR128:$src2)), (PCMPGTBrr VR128:$src1, VR128:$src2)>; - def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, + def : Pat<(v16i8 (X86pcmpgt VR128:$src1, (bc_v16i8 (memopv2i64 addr:$src2)))), (PCMPGTBrm VR128:$src1, addr:$src2)>; - def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)), + def : Pat<(v8i16 (X86pcmpgt VR128:$src1, VR128:$src2)), (PCMPGTWrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, + def : Pat<(v8i16 (X86pcmpgt VR128:$src1, (bc_v8i16 (memopv2i64 addr:$src2)))), (PCMPGTWrm VR128:$src1, addr:$src2)>; - def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)), + def : Pat<(v4i32 (X86pcmpgt VR128:$src1, VR128:$src2)), (PCMPGTDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, + def : Pat<(v4i32 (X86pcmpgt VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))), (PCMPGTDrm VR128:$src1, addr:$src2)>; } @@ -6593,9 +6593,9 @@ let Predicates = [HasAVX] in { defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq, 0>, VEX_4V; - def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)), + def : Pat<(v2i64 (X86pcmpeq VR128:$src1, VR128:$src2)), (VPCMPEQQrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))), + def : Pat<(v2i64 (X86pcmpeq VR128:$src1, (memop addr:$src2))), (VPCMPEQQrm VR128:$src1, addr:$src2)>; } @@ -6624,9 +6624,9 @@ let Predicates = [HasAVX2] in { defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq", int_x86_avx2_pmul_dq>, VEX_4V; - def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)), + def : Pat<(v4i64 (X86pcmpeq VR256:$src1, VR256:$src2)), (VPCMPEQQYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))), + def : Pat<(v4i64 (X86pcmpeq VR256:$src1, (memop addr:$src2))), (VPCMPEQQYrm VR256:$src1, addr:$src2)>; } @@ -6646,9 +6646,9 @@ let Constraints = "$src1 = $dst" in { } let Predicates = [HasSSE41] in { - def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)), + def : Pat<(v2i64 (X86pcmpeq VR128:$src1, VR128:$src2)), (PCMPEQQrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))), + def : Pat<(v2i64 (X86pcmpeq VR128:$src1, (memop addr:$src2))), (PCMPEQQrm VR128:$src1, addr:$src2)>; } @@ -6968,9 +6968,9 @@ let Predicates = [HasAVX] in { defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq, 0>, VEX_4V; - def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)), + def : Pat<(v2i64 (X86pcmpgt VR128:$src1, VR128:$src2)), (VPCMPGTQrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), + def : Pat<(v2i64 (X86pcmpgt VR128:$src1, (memop addr:$src2))), (VPCMPGTQrm VR128:$src1, addr:$src2)>; } @@ -6978,9 +6978,9 @@ let Predicates = [HasAVX2] in { defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>, VEX_4V; - def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)), + def : Pat<(v4i64 (X86pcmpgt VR256:$src1, VR256:$src2)), (VPCMPGTQYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))), + def : Pat<(v4i64 (X86pcmpgt VR256:$src1, (memop addr:$src2))), (VPCMPGTQYrm VR256:$src1, addr:$src2)>; } @@ -6988,9 +6988,9 @@ let Constraints = "$src1 = $dst" in defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>; let Predicates = [HasSSE42] in { - def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)), + def : Pat<(v2i64 (X86pcmpgt VR128:$src1, VR128:$src2)), (PCMPGTQrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), + def : Pat<(v2i64 (X86pcmpgt VR128:$src1, (memop addr:$src2))), (PCMPGTQrm VR128:$src1, addr:$src2)>; }