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Add fake v7 itineraries for now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-21 18:54:14 +00:00
parent 40bbebde9d
commit 6762d91c05
3 changed files with 40 additions and 4 deletions
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10
lib/Target/ARM/ARM.td
View File

@ -103,14 +103,16 @@ def : Processor<"mpcore", V6Itineraries,
[ArchV6, FeatureVFP2]>;
// V6T2 Processors.
def : Processor<"arm1156t2-s", V6Itineraries,
def : Processor<"arm1156t2-s", V6Itineraries,
[ArchV6T2, FeatureThumb2]>;
def : Processor<"arm1156t2f-s", V6Itineraries,
def : Processor<"arm1156t2f-s", V6Itineraries,
[ArchV6T2, FeatureThumb2, FeatureVFP2]>;
// V7 Processors.
def : ProcNoItin<"cortex-a8", [ArchV7A, FeatureThumb2, FeatureNEON]>;
def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
def : Processor<"cortex-a8", CortexA8Itineraries,
[ArchV7A, FeatureThumb2, FeatureNEON]>;
def : Processor<"cortex-a9", V7Itineraries,
[ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===//
// Register File Description

1
lib/Target/ARM/ARMSchedule.td
View File

@ -33,3 +33,4 @@ def IIC_Br : InstrItinClass;
def GenericItineraries : ProcessorItineraries<[]>;
include "ARMScheduleV6.td"
include "ARMScheduleV7.td"

33
lib/Target/ARM/ARMScheduleV7.td Normal file
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@ -0,0 +1,33 @@
//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the ARM v7 processors.
//
//===----------------------------------------------------------------------===//
def V7Itineraries : ProcessorItineraries<[
InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>,
InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>,
InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>,
InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>,
InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>,
InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>,
InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]>
]>;
def CortexA8Itineraries : ProcessorItineraries<[
InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>,
InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>,
InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>,
InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>,
InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>,
InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>,
InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]>
]>;