6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 19:55:11 +00:00
Code Issues Projects Releases Wiki Activity

Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-05 22:15:40 +00:00
parent bc1c98d538
commit 676b2dfd27
1 changed files with 28 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@ -341,20 +341,40 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
bool NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
unsigned FirstOpnd, unsigned NumRegs) {
MachineInstr *RegSeq = 0;
unsigned LastSrcReg = 0;
unsigned LastSubIdx = 0;
for (unsigned R = 0; R < NumRegs; ++R) {
MachineOperand &MO = MI->getOperand(FirstOpnd + R);
assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
unsigned VirtReg = MO.getReg();
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
"expected a virtual register");
if (!MRI->hasOneNonDBGUse(VirtReg))
return false;
MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg);
if (UseMI->getOpcode() != TargetOpcode::REG_SEQUENCE)
return false;
if (RegSeq && RegSeq != UseMI)
return false;
RegSeq = UseMI;
if (MO.isDef()) {
// Feeding into a REG_SEQUENCE.
if (!MRI->hasOneNonDBGUse(VirtReg))
return false;
MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg);
if (!UseMI->isRegSequence())
return false;
if (RegSeq && RegSeq != UseMI)
return false;
RegSeq = UseMI;
} else {
// Extracting from a Q register.
MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
if (!DefMI || !DefMI->isExtractSubreg())
return false;
VirtReg = DefMI->getOperand(1).getReg();
if (LastSrcReg && LastSrcReg != VirtReg)
return false;
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
if (RC != ARM::QPRRegisterClass)
return false;
unsigned SubIdx = DefMI->getOperand(2).getImm();
if (LastSubIdx && LastSubIdx != SubIdx-1)
return false;
LastSubIdx = SubIdx;
}
}
return true;
}