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Put int the getReg cast optimization from x86 so that we generate fewer
move instructions for the register allocator to coalesce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17608 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -502,6 +502,10 @@ unsigned PPC32ISel::getReg(Value *V, MachineBasicBlock *MBB,
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unsigned Reg = makeAnotherReg(V->getType());
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copyConstantToRegister(MBB, IPt, C, Reg);
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return Reg;
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} else if (CastInst *CI = dyn_cast<CastInst>(V)) {
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// Do not emit noop casts at all, unless it's a double -> float cast.
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if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
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return getReg(CI->getOperand(0), MBB, IPt);
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} else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
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unsigned Reg = makeAnotherReg(V->getType());
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unsigned FI = getFixedSizedAllocaFI(AI);
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@ -3129,6 +3133,10 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
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unsigned SrcClass = getClassB(Op->getType());
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unsigned DestClass = getClassB(CI.getType());
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// Noop casts are not emitted: getReg will return the source operand as the
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// register to use for any uses of the noop cast.
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if (DestClass == SrcClass) return;
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// If this is a cast from a 32-bit integer to a Long type, and the only uses
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// of the cast are GEP instructions, then the cast does not need to be
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// generated explicitly, it will be folded into the GEP.
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@ -1,4 +1,6 @@
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TODO:
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* poor switch statement codegen
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* load/store to alloca'd array or struct.
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* implement not-R0 register GPR class
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* implement scheduling info
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* implement do-loop pass
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