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[AArch64] Enhance the load/store optimizer with target-specific alias analysis.
Phabricator: http://reviews.llvm.org/D9863 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237963 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
a33f5160eb
commit
676efa4d56
@ -16,6 +16,7 @@
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#include "AArch64Subtarget.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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@ -483,6 +484,29 @@ static int alignTo(int Num, int PowOf2) {
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return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
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}
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static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
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const AArch64InstrInfo *TII) {
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// One of the instructions must modify memory.
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if (!MIa->mayStore() && !MIb->mayStore())
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return false;
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// Both instructions must be memory operations.
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if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
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return false;
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return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
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}
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static bool mayAlias(MachineInstr *MIa,
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SmallVectorImpl<MachineInstr *> &MemInsns,
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const AArch64InstrInfo *TII) {
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for (auto &MIb : MemInsns)
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if (mayAlias(MIa, MIb, TII))
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return true;
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return false;
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}
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/// findMatchingInsn - Scan the instructions looking for a load/store that can
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/// be combined with the current instruction into a load/store pair.
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MachineBasicBlock::iterator
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@ -518,6 +542,10 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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BitVector ModifiedRegs, UsedRegs;
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.resize(TRI->getNumRegs());
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// Remember any instructions that read/write memory between FirstMI and MI.
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SmallVector<MachineInstr *, 4> MemInsns;
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for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
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MachineInstr *MI = MBBI;
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// Skip DBG_VALUE instructions. Otherwise debug info can affect the
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@ -566,6 +594,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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bool MIIsUnscaled = isUnscaledLdst(MI->getOpcode());
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if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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if (MI->mayLoadOrStore())
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MemInsns.push_back(MI);
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continue;
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}
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// If the alignment requirements of the paired (scaled) instruction
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@ -574,6 +604,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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if (IsUnscaled && EnableAArch64UnscaledMemOp &&
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(alignTo(MinOffset, OffsetStride) != MinOffset)) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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if (MI->mayLoadOrStore())
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MemInsns.push_back(MI);
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continue;
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}
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// If the destination register of the loads is the same register, bail
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@ -581,22 +613,29 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// registers the same is UNPREDICTABLE and will result in an exception.
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if (MayLoad && Reg == MI->getOperand(0).getReg()) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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if (MI->mayLoadOrStore())
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MemInsns.push_back(MI);
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continue;
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}
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// If the Rt of the second instruction was not modified or used between
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// the two instructions, we can combine the second into the first.
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// the two instructions and none of the instructions between the second
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// and first alias with the second, we can combine the second into the
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// first.
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if (!ModifiedRegs[MI->getOperand(0).getReg()] &&
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!UsedRegs[MI->getOperand(0).getReg()]) {
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!UsedRegs[MI->getOperand(0).getReg()] &&
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!mayAlias(MI, MemInsns, TII)) {
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MergeForward = false;
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return MBBI;
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}
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// Likewise, if the Rt of the first instruction is not modified or used
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// between the two instructions, we can combine the first into the
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// second.
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// between the two instructions and none of the instructions between the
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// first and the second alias with the first, we can combine the first
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// into the second.
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if (!ModifiedRegs[FirstMI->getOperand(0).getReg()] &&
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!UsedRegs[FirstMI->getOperand(0).getReg()]) {
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!UsedRegs[FirstMI->getOperand(0).getReg()] &&
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!mayAlias(FirstMI, MemInsns, TII)) {
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MergeForward = true;
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return MBBI;
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}
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@ -605,21 +644,9 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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}
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}
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// If the instruction wasn't a matching load or store, but does (or can)
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// modify memory, stop searching, as we don't have alias analysis or
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// anything like that to tell us whether the access is tromping on the
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// locations we care about. The big one we want to catch is calls.
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//
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// FIXME: Theoretically, we can do better than that for SP and FP based
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// references since we can effectively know where those are touching. It's
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// unclear if it's worth the extra code, though. Most paired instructions
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// will be sequential, perhaps with a few intervening non-memory related
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// instructions.
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if (MI->mayStore() || MI->isCall())
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return E;
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// Likewise, if we're matching a store instruction, we don't want to
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// move across a load, as it may be reading the same location.
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if (FirstMI->mayStore() && MI->mayLoad())
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// If the instruction wasn't a matching load or store. Stop searching if we
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// encounter a call instruction that might modify memory.
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if (MI->isCall())
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return E;
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// Update modified / uses register lists.
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@ -629,6 +656,10 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// return early.
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if (ModifiedRegs[BaseReg])
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return E;
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// Update list of instructions that read/write memory.
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if (MI->mayLoadOrStore())
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MemInsns.push_back(MI);
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}
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return E;
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}
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60
test/CodeGen/AArch64/arm64-ldp-aa.ll
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60
test/CodeGen/AArch64/arm64-ldp-aa.ll
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@ -0,0 +1,60 @@
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; RUN: llc < %s -march=arm64 -enable-misched=false -verify-machineinstrs | FileCheck %s
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; The next set of tests makes sure we can combine the second instruction into
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; the first.
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; CHECK-LABEL: ldp_int_aa
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; CHECK: ldp w8, w9, [x1]
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; CHECK: str w0, [x1, #8]
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; CHECK: ret
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define i32 @ldp_int_aa(i32 %a, i32* %p) nounwind {
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%tmp = load i32, i32* %p, align 4
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%str.ptr = getelementptr inbounds i32, i32* %p, i64 2
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store i32 %a, i32* %str.ptr, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp1 = load i32, i32* %add.ptr, align 4
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%add = add nsw i32 %tmp1, %tmp
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ret i32 %add
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}
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; CHECK-LABEL: ldp_long_aa
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; CHECK: ldp x8, x9, [x1]
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; CHECK: str x0, [x1, #16]
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; CHECK: ret
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define i64 @ldp_long_aa(i64 %a, i64* %p) nounwind {
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%tmp = load i64, i64* %p, align 8
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%str.ptr = getelementptr inbounds i64, i64* %p, i64 2
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store i64 %a, i64* %str.ptr, align 4
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%add.ptr = getelementptr inbounds i64, i64* %p, i64 1
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%tmp1 = load i64, i64* %add.ptr, align 8
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%add = add nsw i64 %tmp1, %tmp
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ret i64 %add
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}
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; CHECK-LABEL: ldp_float_aa
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; CHECK: str s0, [x0, #8]
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; CHECK: ldp s1, s0, [x0]
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; CHECK: ret
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define float @ldp_float_aa(float %a, float* %p) nounwind {
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%tmp = load float, float* %p, align 4
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%str.ptr = getelementptr inbounds float, float* %p, i64 2
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store float %a, float* %str.ptr, align 4
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%add.ptr = getelementptr inbounds float, float* %p, i64 1
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%tmp1 = load float, float* %add.ptr, align 4
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%add = fadd float %tmp, %tmp1
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ret float %add
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}
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; CHECK-LABEL: ldp_double_aa
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; CHECK: str d0, [x0, #16]
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; CHECK: ldp d1, d0, [x0]
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; CHECK: ret
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define double @ldp_double_aa(double %a, double* %p) nounwind {
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%tmp = load double, double* %p, align 8
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%str.ptr = getelementptr inbounds double, double* %p, i64 2
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store double %a, double* %str.ptr, align 4
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%add.ptr = getelementptr inbounds double, double* %p, i64 1
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%tmp1 = load double, double* %add.ptr, align 8
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%add = fadd double %tmp, %tmp1
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ret double %add
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}
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111
test/CodeGen/AArch64/arm64-stp-aa.ll
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111
test/CodeGen/AArch64/arm64-stp-aa.ll
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@ -0,0 +1,111 @@
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; RUN: llc < %s -march=arm64 -enable-misched=false -aarch64-stp-suppress=false -verify-machineinstrs | FileCheck %s
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; The next set of tests makes sure we can combine the second instruction into
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; the first.
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; CHECK-LABEL: stp_int_aa
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; CHECK: stp w0, w1, [x2]
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; CHECK: ldr w0, [x2, #8]
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; CHECK: ret
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define i32 @stp_int_aa(i32 %a, i32 %b, i32* nocapture %p) nounwind {
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store i32 %a, i32* %p, align 4
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%ld.ptr = getelementptr inbounds i32, i32* %p, i64 2
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%tmp = load i32, i32* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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store i32 %b, i32* %add.ptr, align 4
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ret i32 %tmp
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}
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; CHECK-LABEL: stp_long_aa
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; CHECK: stp x0, x1, [x2]
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; CHECK: ldr x0, [x2, #16]
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; CHECK: ret
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define i64 @stp_long_aa(i64 %a, i64 %b, i64* nocapture %p) nounwind {
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store i64 %a, i64* %p, align 8
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%ld.ptr = getelementptr inbounds i64, i64* %p, i64 2
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%tmp = load i64, i64* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds i64, i64* %p, i64 1
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store i64 %b, i64* %add.ptr, align 8
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ret i64 %tmp
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}
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; CHECK-LABEL: stp_float_aa
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; CHECK: stp s0, s1, [x0]
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; CHECK: ldr s0, [x0, #8]
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; CHECK: ret
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define float @stp_float_aa(float %a, float %b, float* nocapture %p) nounwind {
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store float %a, float* %p, align 4
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%ld.ptr = getelementptr inbounds float, float* %p, i64 2
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%tmp = load float, float* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds float, float* %p, i64 1
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store float %b, float* %add.ptr, align 4
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ret float %tmp
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}
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; CHECK-LABEL: stp_double_aa
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; CHECK: stp d0, d1, [x0]
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; CHECK: ldr d0, [x0, #16]
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; CHECK: ret
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define double @stp_double_aa(double %a, double %b, double* nocapture %p) nounwind {
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store double %a, double* %p, align 8
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%ld.ptr = getelementptr inbounds double, double* %p, i64 2
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%tmp = load double, double* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds double, double* %p, i64 1
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store double %b, double* %add.ptr, align 8
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ret double %tmp
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}
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; The next set of tests makes sure we can combine the first instruction into
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; the second.
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; CHECK-LABEL: stp_int_aa_after
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; CHECK: ldr w0, [x3, #4]
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; CHECK: stp w1, w2, [x3]
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; CHECK: ret
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define i32 @stp_int_aa_after(i32 %w0, i32 %a, i32 %b, i32* nocapture %p) nounwind {
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store i32 %a, i32* %p, align 4
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%ld.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp = load i32, i32* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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store i32 %b, i32* %add.ptr, align 4
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ret i32 %tmp
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}
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; CHECK-LABEL: stp_long_aa_after
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; CHECK: ldr x0, [x3, #8]
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; CHECK: stp x1, x2, [x3]
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; CHECK: ret
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define i64 @stp_long_aa_after(i64 %x0, i64 %a, i64 %b, i64* nocapture %p) nounwind {
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store i64 %a, i64* %p, align 8
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%ld.ptr = getelementptr inbounds i64, i64* %p, i64 1
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%tmp = load i64, i64* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds i64, i64* %p, i64 1
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store i64 %b, i64* %add.ptr, align 8
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ret i64 %tmp
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}
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; CHECK-LABEL: stp_float_aa_after
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; CHECK: ldr s0, [x0, #4]
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; CHECK: stp s1, s2, [x0]
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; CHECK: ret
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define float @stp_float_aa_after(float %s0, float %a, float %b, float* nocapture %p) nounwind {
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store float %a, float* %p, align 4
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%ld.ptr = getelementptr inbounds float, float* %p, i64 1
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%tmp = load float, float* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds float, float* %p, i64 1
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store float %b, float* %add.ptr, align 4
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ret float %tmp
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}
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; CHECK-LABEL: stp_double_aa_after
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; CHECK: ldr d0, [x0, #8]
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; CHECK: stp d1, d2, [x0]
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; CHECK: ret
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define double @stp_double_aa_after(double %d0, double %a, double %b, double* nocapture %p) nounwind {
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store double %a, double* %p, align 8
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%ld.ptr = getelementptr inbounds double, double* %p, i64 1
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%tmp = load double, double* %ld.ptr, align 4
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%add.ptr = getelementptr inbounds double, double* %p, i64 1
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store double %b, double* %add.ptr, align 8
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ret double %tmp
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}
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