6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-29 10:32:47 +00:00
Code Issues Projects Releases Wiki Activity

Add some crude approximation for neon load/store instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2010-04-07 18:21:58 +00:00
parent 9113052a1f
commit 67867135ec
1 changed files with 55 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
lib/Target/ARM/ARMScheduleV7.td
View File

@ -320,30 +320,35 @@ def CortexA8Itineraries : ProcessorItineraries<[
// Issue through integer pipeline, and execute in NEON unit. // Issue through integer pipeline, and execute in NEON unit.
// //
// VLD1 // VLD1
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>, InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NLSPipe]>]>, InstrStage<1, [FU_NLSPipe]>]>,
// //
// VLD2 // VLD2
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>, InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>, InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
// //
// VLD3 // VLD3
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>, InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>, InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
// //
// VLD4 // VLD4
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>, InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>, InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
// //
// VST // VST
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>, InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>, InstrStage<1, [FU_LdSt0], 0>,
@ -801,7 +806,56 @@ def CortexA9Itineraries : ProcessorItineraries<[
InstrStage<1, [FU_NPipe]>], [1, 1, 1]>, InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
// NEON // NEON
// Issue through integer pipeline, and execute in NEON unit. // Issue through integer pipeline, and execute in NEON unit.
// FIXME: Neon pipeline and LdSt unit are multiplexed.
// Add some syntactic sugar to model this!
// VLD1
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD1, [InstrStage<1, [FU_DRegsN], 0, Required>,
InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NPipe]>]>,
//
// VLD2
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD2, [InstrStage<1, [FU_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NPipe]>], [2, 2, 1]>,
//
// VLD3
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD3, [InstrStage<1, [FU_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NPipe]>], [2, 2, 2, 1]>,
//
// VLD4
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD4, [InstrStage<1, [FU_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NPipe]>], [2, 2, 2, 2, 1]>,
//
// VST
// FIXME: We don't model this instruction properly
InstrItinData<IIC_VST, [InstrStage<1, [FU_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0], 0>,
InstrStage<1, [FU_NPipe]>]>,
// //
// Double-register Integer Unary // Double-register Integer Unary
InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_DRegsN], 0, Required>, InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_DRegsN], 0, Required>,