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The variable SAR's only take one operand too

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-19 00:31:37 +00:00
parent fd444b2a69
commit 679c408768
1 changed files with 1 additions and 1 deletions
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2
lib/Target/X86/X86ISelPattern.cpp
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@ -3283,7 +3283,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::i32: Opc = X86::SAR32rCL; break;
}
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::SETCC: