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https://github.com/c64scene-ar/llvm-6502.git
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Added phi elimination code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1265 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -943,11 +943,12 @@ ForwardOperand(InstructionNode* treeNode,
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}
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}
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void
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void UltraSparcInstrInfo::
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CreateCopyInstructionsByType(const TargetMachine& target,
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CreateCopyInstructionsByType(const TargetMachine& target,
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Value* src,
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Value* src,
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Instruction* dest,
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Instruction* dest,
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vector<MachineInstr*>& minstrVec)
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vector<MachineInstr*>& minstrVec) const
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{
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{
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bool loadConstantToReg = false;
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bool loadConstantToReg = false;
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@ -1004,6 +1005,7 @@ CreateCopyInstructionsByType(const TargetMachine& target,
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}
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}
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//******************* Externally Visible Functions *************************/
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//******************* Externally Visible Functions *************************/
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@ -2048,7 +2050,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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else
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else
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{
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{
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vector<MachineInstr*> minstrVec;
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vector<MachineInstr*> minstrVec;
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CreateCopyInstructionsByType(target,
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target.getInstrInfo().CreateCopyInstructionsByType(target,
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subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
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subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
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subtreeRoot->getInstruction(), minstrVec);
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subtreeRoot->getInstruction(), minstrVec);
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assert(minstrVec.size() > 0);
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assert(minstrVec.size() > 0);
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@ -139,6 +139,15 @@ public:
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vector<MachineInstr*>& minstrVec,
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vector<MachineInstr*>& minstrVec,
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vector<TmpInstruction*>& tempVec,
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vector<TmpInstruction*>& tempVec,
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TargetMachine& target) const;
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TargetMachine& target) const;
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// create copy instruction(s)
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virtual void
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CreateCopyInstructionsByType(const TargetMachine& target,
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Value* src,
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Instruction* dest,
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vector<MachineInstr*>& minstrVec) const;
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};
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};
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@ -1278,7 +1287,7 @@ private:
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static const int MinStackFrameSize = 176;
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static const int MinStackFrameSize = 176;
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static const int NumFixedOutgoingArgs = 6;
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static const int NumFixedOutgoingArgs = 6;
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static const int SizeOfEachArgOnStack = 8;
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static const int SizeOfEachArgOnStack = 8;
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static const int StaticAreaOffsetFromFP = 0 + OFFSET;
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static const int StaticAreaOffsetFromFP = 0 + OFFSET;
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static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
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static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
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static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
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static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
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static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
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static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
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@ -893,7 +893,6 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
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// register number
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// register number
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
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MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
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const unsigned DestReg,
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const unsigned DestReg,
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const int RegType) const {
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const int RegType) const {
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@ -1040,24 +1039,56 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
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// Following method is Not needed now
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MachineInstr* UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
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//---------------------------------------------------------------------------
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// Generate a copy instruction to copy a value to another. Temporarily
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// used by PhiElimination code.
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//---------------------------------------------------------------------------
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MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
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int RegType = getRegType( Src );
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assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
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MachineInstr * MI = NULL;
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MachineInstr * MI = NULL;
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MI = new MachineInstr(ADD, 3);
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switch( RegType ) {
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
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case IntRegType:
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MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
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MI = new MachineInstr(ADD, 3);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
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MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
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break;
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case FPSingleRegType:
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MI = new MachineInstr(FMOVS, 2);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
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break;
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case FPDoubleRegType:
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MI = new MachineInstr(FMOVD, 2);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
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break;
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default:
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assert(0 && "Unknow RegType in CpValu2Value");
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}
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return MI;
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return MI;
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}
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// This method inserts caller saving/restoring instructons before/after
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// This method inserts caller saving/restoring instructons before/after
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// a call machine instruction.
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// a call machine instruction.
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