mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
596307e133
commit
67a704de03
@ -308,22 +308,25 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b),
|
||||
// These are encoded as unary instructions.
|
||||
let Defs = [FPSCR] in {
|
||||
def VCMPED : ADuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
|
||||
(outs),(ins DPR:$Dd, DPR:$Dm),
|
||||
(outs), (ins DPR:$Dd, DPR:$Dm),
|
||||
IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
|
||||
[(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
|
||||
|
||||
def VCMPES : ASuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
|
||||
(outs),(ins SPR:$Sd, SPR:$Sm),
|
||||
(outs), (ins SPR:$Sd, SPR:$Sm),
|
||||
IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
|
||||
[(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
|
||||
|
||||
def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
|
||||
IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
// FIXME: Verify encoding after integrated assembler is working.
|
||||
def VCMPD : ADuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
|
||||
(outs), (ins DPR:$Dd, DPR:$Dm),
|
||||
IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
|
||||
def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
|
||||
IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
def VCMPS : ASuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
|
||||
(outs), (ins SPR:$Sd, SPR:$Sm),
|
||||
IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -357,13 +360,22 @@ def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
|
||||
let Inst{5} = 0;
|
||||
}
|
||||
|
||||
def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
|
||||
IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
// FIXME: Verify encoding after integrated assembler is working.
|
||||
def VCMPZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
|
||||
(outs), (ins DPR:$Dd),
|
||||
IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
|
||||
[/* For disassembly only; pattern left blank */]> {
|
||||
let Inst{3-0} = 0b0000;
|
||||
let Inst{5} = 0;
|
||||
}
|
||||
|
||||
def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a),
|
||||
IIC_fpCMP32, "vcmp", ".f32\t$a, #0",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
def VCMPZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
|
||||
(outs), (ins SPR:$Sd),
|
||||
IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
|
||||
[/* For disassembly only; pattern left blank */]> {
|
||||
let Inst{3-0} = 0b0000;
|
||||
let Inst{5} = 0;
|
||||
}
|
||||
}
|
||||
|
||||
def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
|
||||
@ -404,6 +416,7 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
|
||||
|
||||
// Between half-precision and single-precision. For disassembly only.
|
||||
|
||||
// FIXME: Verify encoding after integrated assembler is working.
|
||||
def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
|
||||
/* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
@ -426,16 +439,6 @@ def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
|
||||
/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
|
||||
[/* For disassembly only; pattern left blank */]>;
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
|
||||
(outs DPR:$Dd), (ins DPR:$Dm),
|
||||
IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
|
||||
|
||||
def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
|
||||
} // neverHasSideEffects
|
||||
|
||||
def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
|
||||
(outs DPR:$Dd), (ins DPR:$Dm),
|
||||
IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
|
||||
@ -456,6 +459,16 @@ def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
|
||||
IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
|
||||
(outs DPR:$Dd), (ins DPR:$Dm),
|
||||
IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
|
||||
|
||||
def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
|
||||
} // neverHasSideEffects
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP <-> GPR Copies. Int <-> FP Conversions.
|
||||
//
|
||||
@ -505,102 +518,168 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
|
||||
// FMRDH: SPR -> GPR
|
||||
// FMRDL: SPR -> GPR
|
||||
// FMRRS: SPR -> GPR
|
||||
// FMRX : SPR system reg -> GPR
|
||||
|
||||
// FMRX: SPR system reg -> GPR
|
||||
// FMSRR: GPR -> SPR
|
||||
|
||||
// FMXR: GPR -> VFP system reg
|
||||
// FMXR: GPR -> VFP system reg
|
||||
|
||||
|
||||
// Int to FP:
|
||||
// Int -> FP:
|
||||
|
||||
def VSITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
|
||||
(outs DPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
|
||||
[(set DPR:$dst, (f64 (arm_sitof SPR:$a)))]> {
|
||||
class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
|
||||
bits<4> opcod4, dag oops, dag iops,
|
||||
InstrItinClass itin, string opc, string asm,
|
||||
list<dag> pattern>
|
||||
: AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
|
||||
pattern> {
|
||||
// Instruction operands.
|
||||
bits<5> Dd;
|
||||
bits<5> Sm;
|
||||
|
||||
// Encode instruction operands.
|
||||
let Inst{3-0} = Sm{4-1};
|
||||
let Inst{5} = Sm{0};
|
||||
let Inst{15-12} = Dd{3-0};
|
||||
let Inst{22} = Dd{4};
|
||||
}
|
||||
|
||||
class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
|
||||
bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
|
||||
string opc, string asm, list<dag> pattern>
|
||||
: AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
|
||||
pattern> {
|
||||
// Instruction operands.
|
||||
bits<5> Sd;
|
||||
bits<5> Sm;
|
||||
|
||||
// Encode instruction operands.
|
||||
let Inst{3-0} = Sm{4-1};
|
||||
let Inst{5} = Sm{0};
|
||||
let Inst{15-12} = Sd{4-1};
|
||||
let Inst{22} = Sd{0};
|
||||
}
|
||||
|
||||
def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
|
||||
(outs DPR:$Dd), (ins SPR:$Sm),
|
||||
IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
|
||||
[(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
|
||||
let Inst{7} = 1; // s32
|
||||
}
|
||||
|
||||
def VSITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
|
||||
(outs SPR:$dst),(ins SPR:$a),
|
||||
IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
|
||||
[(set SPR:$dst, (arm_sitof SPR:$a))]> {
|
||||
def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
|
||||
(outs SPR:$Sd),(ins SPR:$Sm),
|
||||
IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
|
||||
let Inst{7} = 1; // s32
|
||||
}
|
||||
|
||||
def VUITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
|
||||
(outs DPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
|
||||
[(set DPR:$dst, (f64 (arm_uitof SPR:$a)))]> {
|
||||
def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
|
||||
(outs DPR:$Dd), (ins SPR:$Sm),
|
||||
IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
|
||||
[(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
|
||||
let Inst{7} = 0; // u32
|
||||
}
|
||||
|
||||
def VUITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
|
||||
(outs SPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
|
||||
[(set SPR:$dst, (arm_uitof SPR:$a))]> {
|
||||
def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
|
||||
let Inst{7} = 0; // u32
|
||||
}
|
||||
|
||||
// FP to Int:
|
||||
// FP -> Int:
|
||||
|
||||
class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
|
||||
bits<4> opcod4, dag oops, dag iops,
|
||||
InstrItinClass itin, string opc, string asm,
|
||||
list<dag> pattern>
|
||||
: AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
|
||||
pattern> {
|
||||
// Instruction operands.
|
||||
bits<5> Sd;
|
||||
bits<5> Dm;
|
||||
|
||||
// Encode instruction operands.
|
||||
let Inst{3-0} = Dm{3-0};
|
||||
let Inst{5} = Dm{4};
|
||||
let Inst{15-12} = Sd{4-1};
|
||||
let Inst{22} = Sd{0};
|
||||
}
|
||||
|
||||
class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
|
||||
bits<4> opcod4, dag oops, dag iops,
|
||||
InstrItinClass itin, string opc, string asm,
|
||||
list<dag> pattern>
|
||||
: AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
|
||||
pattern> {
|
||||
// Instruction operands.
|
||||
bits<5> Sd;
|
||||
bits<5> Sm;
|
||||
|
||||
// Encode instruction operands.
|
||||
let Inst{3-0} = Sm{4-1};
|
||||
let Inst{5} = Sm{0};
|
||||
let Inst{15-12} = Sd{4-1};
|
||||
let Inst{22} = Sd{0};
|
||||
}
|
||||
|
||||
// Always set Z bit in the instruction, i.e. "round towards zero" variants.
|
||||
|
||||
def VTOSIZD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
|
||||
(outs SPR:$dst), (ins DPR:$a),
|
||||
IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
|
||||
[(set SPR:$dst, (arm_ftosi (f64 DPR:$a)))]> {
|
||||
def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
|
||||
(outs SPR:$Sd), (ins DPR:$Dm),
|
||||
IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
|
||||
[(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
}
|
||||
|
||||
def VTOSIZS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
|
||||
(outs SPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
|
||||
[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
|
||||
def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
}
|
||||
|
||||
def VTOUIZD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
|
||||
(outs SPR:$dst), (ins DPR:$a),
|
||||
IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
|
||||
[(set SPR:$dst, (arm_ftoui (f64 DPR:$a)))]> {
|
||||
def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
|
||||
(outs SPR:$Sd), (ins DPR:$Dm),
|
||||
IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
|
||||
[(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
}
|
||||
|
||||
def VTOUIZS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
|
||||
(outs SPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
|
||||
[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
|
||||
def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
|
||||
let Inst{7} = 1; // Z bit
|
||||
}
|
||||
|
||||
// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
|
||||
// For disassembly only.
|
||||
let Uses = [FPSCR] in {
|
||||
def VTOSIRD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
|
||||
(outs SPR:$dst), (ins DPR:$a),
|
||||
IIC_fpCVTDI, "vcvtr", ".s32.f64\t$dst, $a",
|
||||
[(set SPR:$dst, (int_arm_vcvtr (f64 DPR:$a)))]> {
|
||||
// FIXME: Verify encoding after integrated assembler is working.
|
||||
def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
|
||||
(outs SPR:$Sd), (ins DPR:$Dm),
|
||||
IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
|
||||
[(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
|
||||
let Inst{7} = 0; // Z bit
|
||||
}
|
||||
|
||||
def VTOSIRS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
|
||||
(outs SPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTSI, "vcvtr", ".s32.f32\t$dst, $a",
|
||||
[(set SPR:$dst, (int_arm_vcvtr SPR:$a))]> {
|
||||
def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
|
||||
let Inst{7} = 0; // Z bit
|
||||
}
|
||||
|
||||
def VTOUIRD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
|
||||
(outs SPR:$dst), (ins DPR:$a),
|
||||
IIC_fpCVTDI, "vcvtr", ".u32.f64\t$dst, $a",
|
||||
[(set SPR:$dst, (int_arm_vcvtru (f64 DPR:$a)))]> {
|
||||
def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
|
||||
(outs SPR:$Sd), (ins DPR:$Dm),
|
||||
IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
|
||||
[(set SPR:$Sd, (int_arm_vcvtru (f64 DPR:$Dm)))]> {
|
||||
let Inst{7} = 0; // Z bit
|
||||
}
|
||||
|
||||
def VTOUIRS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
|
||||
(outs SPR:$dst), (ins SPR:$a),
|
||||
IIC_fpCVTSI, "vcvtr", ".u32.f32\t$dst, $a",
|
||||
[(set SPR:$dst, (int_arm_vcvtru SPR:$a))]> {
|
||||
def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
|
||||
(outs SPR:$Sd), (ins SPR:$Sm),
|
||||
IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
|
||||
[(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
|
||||
let Inst{7} = 0; // Z bit
|
||||
}
|
||||
}
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
define double @f1(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f1
|
||||
; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
|
||||
; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
|
||||
%add = fadd double %a, %b
|
||||
ret double %add
|
||||
}
|
||||
@ -17,7 +17,7 @@ entry:
|
||||
define float @f2(float %a, float %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f2
|
||||
; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
|
||||
; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
|
||||
%add = fadd float %a, %b
|
||||
ret float %add
|
||||
}
|
||||
@ -25,7 +25,7 @@ entry:
|
||||
define double @f3(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f3
|
||||
; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
|
||||
; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
|
||||
%sub = fsub double %a, %b
|
||||
ret double %sub
|
||||
}
|
||||
@ -33,7 +33,7 @@ entry:
|
||||
define float @f4(float %a, float %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f4
|
||||
; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
|
||||
; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
|
||||
%sub = fsub float %a, %b
|
||||
ret float %sub
|
||||
}
|
||||
@ -41,7 +41,7 @@ entry:
|
||||
define double @f5(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f5
|
||||
; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
|
||||
; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
|
||||
%div = fdiv double %a, %b
|
||||
ret double %div
|
||||
}
|
||||
@ -49,7 +49,7 @@ entry:
|
||||
define float @f6(float %a, float %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f6
|
||||
; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
|
||||
; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
|
||||
%div = fdiv float %a, %b
|
||||
ret float %div
|
||||
}
|
||||
@ -57,7 +57,7 @@ entry:
|
||||
define double @f7(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f7
|
||||
; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
|
||||
; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
|
||||
%mul = fmul double %a, %b
|
||||
ret double %mul
|
||||
}
|
||||
@ -65,7 +65,7 @@ entry:
|
||||
define float @f8(float %a, float %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f8
|
||||
; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
|
||||
; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
|
||||
%mul = fmul float %a, %b
|
||||
ret float %mul
|
||||
}
|
||||
@ -73,7 +73,7 @@ entry:
|
||||
define double @f9(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f9
|
||||
; CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
|
||||
; CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
|
||||
%mul = fmul double %a, %b
|
||||
%sub = fsub double -0.000000e+00, %mul
|
||||
ret double %sub
|
||||
@ -82,7 +82,7 @@ entry:
|
||||
define void @f10(float %a, float %b, float* %c) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f10
|
||||
; CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
|
||||
; CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
|
||||
%mul = fmul float %a, %b
|
||||
%sub = fsub float -0.000000e+00, %mul
|
||||
store float %sub, float* %c, align 4
|
||||
@ -92,7 +92,7 @@ entry:
|
||||
define i1 @f11(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f11
|
||||
; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
|
||||
; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
|
||||
%cmp = fcmp oeq double %a, %b
|
||||
ret i1 %cmp
|
||||
}
|
||||
@ -100,7 +100,7 @@ entry:
|
||||
define i1 @f12(float %a, float %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f12
|
||||
; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
|
||||
; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
|
||||
%cmp = fcmp oeq float %a, %b
|
||||
ret i1 %cmp
|
||||
}
|
||||
@ -108,7 +108,7 @@ entry:
|
||||
define i1 @f13(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f13
|
||||
; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
|
||||
; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
|
||||
%cmp = fcmp oeq double %a, 0.000000e+00
|
||||
ret i1 %cmp
|
||||
}
|
||||
@ -116,7 +116,7 @@ entry:
|
||||
define i1 @f14(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f14
|
||||
; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
|
||||
; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
|
||||
%cmp = fcmp oeq float %a, 0.000000e+00
|
||||
ret i1 %cmp
|
||||
}
|
||||
@ -124,7 +124,7 @@ entry:
|
||||
define double @f15(double %a) nounwind {
|
||||
entry:
|
||||
; CHECK: f15
|
||||
; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
|
||||
; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
|
||||
%call = tail call double @fabsl(double %a)
|
||||
ret double %call
|
||||
}
|
||||
@ -144,7 +144,7 @@ declare float @fabsf(float)
|
||||
define float @f17(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f17
|
||||
; CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
|
||||
; CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
|
||||
%conv = fptrunc double %a to float
|
||||
ret float %conv
|
||||
}
|
||||
@ -152,7 +152,7 @@ entry:
|
||||
define double @f18(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f18
|
||||
; CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
|
||||
; CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
|
||||
%conv = fpext float %a to double
|
||||
ret double %conv
|
||||
}
|
||||
@ -160,7 +160,7 @@ entry:
|
||||
define double @f19(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f19
|
||||
; CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
|
||||
; CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
|
||||
%sub = fsub double -0.000000e+00, %a
|
||||
ret double %sub
|
||||
}
|
||||
@ -176,7 +176,7 @@ entry:
|
||||
define double @f21(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f21
|
||||
; CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
|
||||
; CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
|
||||
%call = tail call double @sqrtl(double %a) nounwind
|
||||
ret double %call
|
||||
}
|
||||
@ -186,9 +186,73 @@ declare double @sqrtl(double) readnone
|
||||
define float @f22(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f22
|
||||
; CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
|
||||
; CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
|
||||
%call = tail call float @sqrtf(float %a) nounwind
|
||||
ret float %call
|
||||
}
|
||||
|
||||
declare float @sqrtf(float) readnone
|
||||
|
||||
define double @f23(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f23
|
||||
; CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
|
||||
%conv = sitofp i32 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
|
||||
define float @f24(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f24
|
||||
; CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
|
||||
%conv = sitofp i32 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
define double @f25(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f25
|
||||
; CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
|
||||
%conv = uitofp i32 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
|
||||
define float @f26(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f26
|
||||
; CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
|
||||
%conv = uitofp i32 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
define i32 @f27(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f27
|
||||
; CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
|
||||
%conv = fptosi double %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define i32 @f28(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f28
|
||||
; CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
|
||||
%conv = fptosi float %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define i32 @f29(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f29
|
||||
; CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
|
||||
%conv = fptoui double %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define i32 @f30(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f30
|
||||
; CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
|
||||
%conv = fptoui float %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user