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synced 2024-08-24 09:29:42 +00:00
PTX: Use .param space for parameters in device functions for SM >= 2.0
FIXME: DCE is eliminating the final st.param.x calls, figure out why git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133732 91177308-0d34-0410-b5e6-96231b3b80d8
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28578e3137
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@ -417,6 +417,7 @@ void PTXAsmPrinter::EmitFunctionDeclaration() {
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const PTXMachineFunctionInfo *MFI = MF->getInfo<PTXMachineFunctionInfo>();
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const bool isKernel = MFI->isKernel();
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const PTXSubtarget& ST = TM.getSubtarget<PTXSubtarget>();
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std::string decl = isKernel ? ".entry" : ".func";
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@ -452,7 +453,7 @@ void PTXAsmPrinter::EmitFunctionDeclaration() {
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if (i != b) {
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decl += ", ";
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}
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if (isKernel) {
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if (isKernel || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
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decl += ".param .b";
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decl += utostr(*i);
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decl += " ";
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@ -15,6 +15,7 @@
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#include "PTXTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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@ -42,7 +43,8 @@ class PTXDAGToDAGISel : public SelectionDAGISel {
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private:
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SDNode *SelectREAD_PARAM(SDNode *Node);
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//SDNode *SelectSTORE_PARAM(SDNode *Node);
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// We need this only because we can't match intruction BRAdp
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// pattern (PTXbrcond bb:$d, ...) in PTXInstrInfo.td
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SDNode *SelectBRCOND(SDNode *Node);
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@ -69,6 +71,8 @@ SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
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switch (Node->getOpcode()) {
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case PTXISD::READ_PARAM:
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return SelectREAD_PARAM(Node);
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// case PTXISD::STORE_PARAM:
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// return SelectSTORE_PARAM(Node);
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case ISD::BRCOND:
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return SelectBRCOND(Node);
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default:
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@ -86,20 +90,15 @@ SDNode *PTXDAGToDAGISel::SelectREAD_PARAM(SDNode *Node) {
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if (Node->getValueType(0) == MVT::i16) {
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opcode = PTX::LDpiU16;
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}
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else if (Node->getValueType(0) == MVT::i32) {
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} else if (Node->getValueType(0) == MVT::i32) {
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opcode = PTX::LDpiU32;
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}
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else if (Node->getValueType(0) == MVT::i64) {
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} else if (Node->getValueType(0) == MVT::i64) {
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opcode = PTX::LDpiU64;
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}
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else if (Node->getValueType(0) == MVT::f32) {
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} else if (Node->getValueType(0) == MVT::f32) {
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opcode = PTX::LDpiF32;
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}
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else if (Node->getValueType(0) == MVT::f64) {
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} else if (Node->getValueType(0) == MVT::f64) {
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opcode = PTX::LDpiF64;
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}
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else {
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} else {
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llvm_unreachable("Unknown parameter type for ld.param");
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}
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@ -107,6 +106,42 @@ SDNode *PTXDAGToDAGISel::SelectREAD_PARAM(SDNode *Node) {
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GetPTXMachineNode(CurDAG, opcode, dl, Node->getValueType(0), index);
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}
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// SDNode *PTXDAGToDAGISel::SelectSTORE_PARAM(SDNode *Node) {
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// SDValue Chain = Node->getOperand(0);
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// SDValue index = Node->getOperand(1);
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// SDValue value = Node->getOperand(2);
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// DebugLoc dl = Node->getDebugLoc();
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// unsigned opcode;
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// if (index.getOpcode() != ISD::TargetConstant)
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// llvm_unreachable("STORE_PARAM: index is not ISD::TargetConstant");
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// if (value->getValueType(0) == MVT::i16) {
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// opcode = PTX::STpiU16;
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// } else if (value->getValueType(0) == MVT::i32) {
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// opcode = PTX::STpiU32;
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// } else if (value->getValueType(0) == MVT::i64) {
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// opcode = PTX::STpiU64;
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// } else if (value->getValueType(0) == MVT::f32) {
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// opcode = PTX::STpiF32;
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// } else if (value->getValueType(0) == MVT::f64) {
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// opcode = PTX::STpiF64;
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// } else {
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// llvm_unreachable("Unknown parameter type for st.param");
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// }
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// SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
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// SDValue PredReg = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
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// SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32);
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// SDValue Ops[] = { Chain, index, value, PredReg, PredOp };
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// //SDNode *RetNode = PTXInstrInfo::
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// // GetPTXMachineNode(CurDAG, opcode, dl, VTs, index, value);
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// SDNode *RetNode = CurDAG->getMachineNode(opcode, dl, VTs, Ops, array_lengthof(Ops));
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// DEBUG(dbgs() << "SelectSTORE_PARAM: Selected: ");
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// RetNode->dumpr(CurDAG);
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// return RetNode;
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// }
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SDNode *PTXDAGToDAGISel::SelectBRCOND(SDNode *Node) {
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assert(Node->getNumOperands() >= 3);
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@ -15,6 +15,7 @@
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#include "PTXISelLowering.h"
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#include "PTXMachineFunctionInfo.h"
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#include "PTXRegisterInfo.h"
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#include "PTXSubtarget.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -106,6 +107,8 @@ const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "PTXISD::COPY_ADDRESS";
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case PTXISD::READ_PARAM:
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return "PTXISD::READ_PARAM";
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case PTXISD::STORE_PARAM:
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return "PTXISD::STORE_PARAM";
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case PTXISD::EXIT:
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return "PTXISD::EXIT";
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case PTXISD::RET:
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@ -192,6 +195,7 @@ SDValue PTXTargetLowering::
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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MachineFunction &MF = DAG.getMachineFunction();
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const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
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PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
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switch (CallConv) {
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@ -206,11 +210,16 @@ SDValue PTXTargetLowering::
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break;
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}
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if (MFI->isKernel()) {
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// For kernel functions, we just need to emit the proper READ_PARAM ISDs
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// We do one of two things here:
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// IsKernel || SM >= 2.0 -> Use param space for arguments
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// SM < 2.0 -> Use registers for arguments
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if (MFI->isKernel() || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
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// We just need to emit the proper READ_PARAM ISDs
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for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
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assert(Ins[i].VT != MVT::i1 && "Kernels cannot take pred operands");
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assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
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"Kernels cannot take pred operands");
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SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, Ins[i].VT, Chain,
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DAG.getTargetConstant(i, MVT::i32));
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@ -299,31 +308,49 @@ SDValue PTXTargetLowering::
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MachineFunction& MF = DAG.getMachineFunction();
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PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
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SDValue Flag;
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CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
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if (ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
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// For SM 2.0+, we return arguments in the param space
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue ParamIndex = DAG.getTargetConstant(i, MVT::i32);
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SDValue Ops[] = { Chain, ParamIndex, OutVals[i], Flag };
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Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, VTs, Ops,
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Flag.getNode() ? 4 : 3);
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Flag = Chain.getValue(1);
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// Instead of storing a physical register in our argument list, we just
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// store the total size of the parameter, in bits. The ASM printer
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// knows how to process this.
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MFI->addRetReg(Outs[i].VT.getStoreSizeInBits());
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}
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} else {
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// For SM < 2.0, we return arguments in registers
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
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CCValAssign& VA = RVLocs[i];
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCValAssign& VA = RVLocs[i];
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assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
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assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
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unsigned Reg = VA.getLocReg();
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unsigned Reg = VA.getLocReg();
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DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
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DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
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Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
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Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad
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Flag = Chain.getValue(1);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad
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Flag = Chain.getValue(1);
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MFI->addRetReg(Reg);
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MFI->addRetReg(Reg);
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}
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}
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if (Flag.getNode() == 0) {
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@ -25,11 +25,12 @@ namespace PTXISD {
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enum NodeType {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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READ_PARAM,
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STORE_PARAM,
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EXIT,
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RET,
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COPY_ADDRESS
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};
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} // namespace PTXISD
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} // namespace PTXISD
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class PTXTargetLowering : public TargetLowering {
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public:
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@ -180,10 +180,15 @@ def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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: SDNode<"PTXISD::RET", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def PTXcopyaddress
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: SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
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def PTXstoreparam
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: SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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@ -816,7 +821,7 @@ defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
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defm LDl : PTX_LD_ALL<"ld.local", load_local>;
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defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
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// This is a special instruction that is manually inserted for kernel parameters
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// This is a special instruction that is manually inserted for parameters
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def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
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"ld.param.u16\t$d, [$a]", []>;
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def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
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@ -828,6 +833,23 @@ def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
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def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
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"ld.param.f64\t$d, [$a]", []>;
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// def STpiPred : InstPTX<(outs), (ins i1imm:$d, RegPred:$a),
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// "st.param.pred\t[$d], $a",
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// [(PTXstoreparam imm:$d, RegPred:$a)]>;
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// def STpiU16 : InstPTX<(outs), (ins i16imm:$d, RegI16:$a),
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// "st.param.u16\t[$d], $a",
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// [(PTXstoreparam imm:$d, RegI16:$a)]>;
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def STpiU32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
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"st.param.u32\t[$d], $a",
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[(PTXstoreparam timm:$d, RegI32:$a)]>;
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// def STpiU64 : InstPTX<(outs), (ins i64imm:$d, RegI64:$a),
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// "st.param.u64\t[$d], $a",
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// [(PTXstoreparam imm:$d, RegI64:$a)]>;
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// def STpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a),
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// "st.param.f32\t[$d], $a", []>;
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// def STpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a),
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// "st.param.f64\t[$d], $a", []>;
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// Stores
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defm STg : PTX_ST_ALL<"st.global", store_global>;
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defm STl : PTX_ST_ALL<"st.local", store_local>;
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@ -18,7 +18,7 @@
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namespace llvm {
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class PTXSubtarget : public TargetSubtarget {
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private:
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public:
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/**
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* Enumeration of Shader Models supported by the back-end.
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@ -41,6 +41,8 @@ namespace llvm {
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PTX_VERSION_2_3 /*< PTX Version 2.3 */
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};
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private:
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/// Shader Model supported on the target GPU.
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PTXShaderModelEnum PTXShaderModel;
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@ -58,8 +60,10 @@ namespace llvm {
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bool Is64Bit;
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public:
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PTXSubtarget(const std::string &TT, const std::string &FS, bool is64Bit);
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// Target architecture accessors
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std::string getTargetString() const;
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std::string getPTXVersionString() const;
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@ -80,6 +84,9 @@ namespace llvm {
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bool supportsPTX23() const { return PTXVersion >= PTX_VERSION_2_3; }
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PTXShaderModelEnum getShaderModel() const { return PTXShaderModel; }
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std::string ParseSubtargetFeatures(const std::string &FS,
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const std::string &CPU);
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}; // class PTXSubtarget
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